Doulos is looking forward to being Gold Sponsors of SNUG India at the Leela Palace, Bangalore on June 12th.

Find out about the updated Doulos SystemVerilog portfolio including the new 4-day UVM Adopter Class, the latest scheduled courses running in Bangalore and news about on-line training...

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As Gold sponsors of this year's SNUG events, Doulos will again be exhibiting in Grenoble in June.

Visit the Doulos booth at the Grenoble World Trade Center on June 11 to discover the enhanced SystemVerilog portfolio which is now fully available.

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                        2013

Doulos will present an entire day of world-class training at DAC 2013 available in four tracks covering SystemVerilog Design, SystemVerilog Verification, ARM Cortex Processor Family and ESL & SystemC!

Find out more about "Thursday is Training Day" and register for special offers »

As Gold sponsors of this year's SNUG events, Doulos will again be exhibiting and presenting in Reading and Munich in May.

Visit the Doulos booth at the Munich City Hilton Hotel on May 14 and the Hilton Reading Hotel on May 16 to discover how the Doulos SystemVerilog portfolio is developing.

Principle Member of Technical Staff, Dr David Long, will be presenting Making the most of SystemVerilog and UVM: Hints and Tips for new users. This paper is intended to give guidance to engineers about some useful features of both SystemVerilog and UVM that are often overlooked, used incorrectly or simply avoided because they are perceived as being too hard to understand. 

View full details of this paper »
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                        2013

Find out about how the Doulos SystemVerilog portfolio is developing at SNUG Silicon Valley at the Santa Clara Convention Centre, CA on March 25.

Doug Smith will also be presenting Random Stability in SystemVerilog. This paper discusses random stability, especially the use of good random seeds and locking down random number generator (RNG) seeding for test reproducibility.

View full details of this paper »
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Webinar: Software development from ARM Cortex-M to Cortex-A
Start date: March 8, 2013
Duration: x1 1 hour session (international zones covered)
Presenter: Dr David Cabanis, Senior Member of Technical Staff
Summary:
This webinar will highlight the differences between Cortex-M and Cortex-A based software development and demonstrate the basic requirements for creating a bare metal application on a Cortex-A9 core using the  Xilinx QEMU for Zynq™ Virtual Platform as an example.

Webinar: How to take advantage of UVM-style run-time configuration in VHDL
Start date: March 1, 2013
Duration: x1 1 hour session (international zones covered)
Presenter: Alan Fitch, Principal Member of Technical Staff
Summary:
Do you have to change to UVM just to get run-time configuration? This webinar is for you if you're interested in how to run multiple different tests without the overhead of compiling.

Find out about how the Doulos SystemVerilog portfolio is developing at DVCon at the DoubleTree Hotel in San Jose from February 25.

Doulos CTO, John Aynsley and Senior Member of technical Staff, David C Black will also be involved in a number of technical presentations...

Webinar: First Steps with UVM
Start date: February 15, 2013
Duration: x1 1 hour session (international zones covered)
Presenter: John Aynsley, Doulos CTO
Summary:
This webinar will get you started with UVM by walking through some very simple examples of working UVM code, explaining what is happening and highlighting both best practice and common pitfalls as we go.

Webinar: Advanced VHDL Verification - OSVVM and more...
Start date: December 7, 2012
Duration: x1 1 hour session (international zones covered)
Presenter: Alan Fitch, Principal Member of Technical Staff
Summary:
Are you using VHDL for verification of complex designs, and wondering if you should move to UVM and SystemVerilog? This webinar will introduce you to Open Source VHDL Verification Methodology (OSVVM): what it does, how to use it, and how it compares with UVM.