Presented by Doulos & Mentor Graphics

The last few years have seen the maturing of standard languages for hardware design, verification, and systems modelling. The focus has now moved on to consider how multiple languages can be applied in systematic ways as part of a disciplined and effective functional verification methodology. This workshop is suitable for engineers and engineering management who require a technical introduction to the new developments in verification methodology.

This workshop will discuss functional verification methodologies as exemplified by Mentor Graphics' Advanced Verification Methodology (AVM). Assertion Based Verification, Coverage Driven Verification, Test Bench Automation, and Transaction Level Modelling will be introduced and positioned within the context of the verification flow. The workshop will illustrate how the underlying language mechanisms of SystemVerilog and SystemC get harnessed to create a unified verification methodology.