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Building Re-usable Verification Components in the Language of Your Choice within a Plan-to-Closure Flow
Presented by Doulos & Cadence
Today, verification re-use is as critical as design re-use in the success of complex SoC projects. Equally important is the need for a plan and metric driven approach to the successful achievement of verification closure in a predictable manner. Project teams need a methodology that incorporates re-use and various languages in a plan-to-closure flow.
The workshop will describe how to build reusable verification components covering subjects like coding styles and structure, handling clocks and resets, messaging and logging services, test interfaces, and checking and coverage. It will describe how to use IEEE languages- e, SystemVerilog, and SystemC, either together or separately, to build re-usable verification components within the Cadence® Incisive® Plan-to-Closure Methodology. This methodology spans the full verification process from automated verification plans to system-level verification closure. The workshop will also illustrate how to make effective use of verification plans and metrics to reach closure.
The workshop will describe how to build reusable verification components covering subjects like coding styles and structure, handling clocks and resets, messaging and logging services, test interfaces, and checking and coverage. It will describe how to use IEEE languages- e, SystemVerilog, and SystemC, either together or separately, to build re-usable verification components within the Cadence® Incisive® Plan-to-Closure Methodology. This methodology spans the full verification process from automated verification plans to system-level verification closure. The workshop will also illustrate how to make effective use of verification plans and metrics to reach closure.
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