Get to grips with the latest know-how on ESL and verification methodology at the DAC Solutions Workshops. Now in its 3rd series at DAC, these fast-paced 2 hour technical seminars (including lunch) have been put together by Doulos in co-operation with leading vendors.

This year's lunch-time series is presented in conjunction with Cadence, CoWare, Mentor Graphics, Synopsys and The MathWorks.

Register NOW and win...

..an early registration bonus. Your choice of the engineers must have project reference - the Doulos Golden Reference Guide (worth $50). Available for Verilog, SystemVerilog, SystemVerilog Assertions, SystemC, e, PSL or VHDL. Register before June 1st to receive one copy when you attend a workshop.

Click on the abstract links below for workshop details and registration.

Using SystemC and SystemVerilog together in an Advanced Verification Methodology (AVM)

Presented by Doulos & Mentor Graphics
Monday June 4th, 12:00 - 2pm
Lunch included
Abstract

Standards and Guidelines for SystemC Transaction Level Modeling

Presented by Doulos & CoWare
Tuesday 5th June, 11:00 - 12:30pm
Lunch included
Abstract

Adopting a Plan-to-Closure Methodology across Design Teams and Verification Teams

Presented by Doulos & Cadence
Tuesday 5th June, 12:45 - 2:45pm
Lunch included
Abstract

Using VMM Applications for Increased Verification Productivity

Presented by Doulos & Synopsys
Thursday 7th June, 11:00 - 1pm
Lunch included
Abstract

Rapid DSP Implementation Techniques for FPGAs

Presented by Doulos Certified Training Provider ALSE & The MathWorks
Thursday 7th June, 11:00 - 1pm
Lunch included
Abstract