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Rapid DSP Implementation Techniques for FPGAs
Thursday 19th April, 13:00 - 14:30
Presented by Doulos partners, ALSE & The MathWorks
Lunch 12:30 - 13:00
€50
Presented by Doulos partners, ALSE & The MathWorks
Lunch 12:30 - 13:00
€50
As FPGAs are becoming more widely used, two distinct challenges are emerging. Firstly, designs are becoming harder to implement due to increased silicon and system complexity. Secondly new groups of users are emerging who want to use FPGAs, but lack HDL programming skills. These two very different user communities are looking for news ways to design DSP systems on FPGAs.
Both communities are looking at increasing engineering productivity, and it is widely acknowledged that this can best be done by raising the level of design abstraction. However there are concerns that raising the level of abstraction will impact design efficiency and quality.
This workshop will examine some of the issues involved in creating DSP systems on FPGAs, and will show how the abstraction level (and hence developer productivity) can be raised without compromising efficiency and quality. The workshop will discuss design flows and techniques for implementing DSP systems in FPGAs, including fixed and floating point modeling, tuning algorithms for efficient FPGA implementation, automatic HDL code generation, and closing the verification loop. Delegates will be shown practical examples of implementation flows starting from system models captured using MATLAB® and Simulink® from The MathWorks.
Both communities are looking at increasing engineering productivity, and it is widely acknowledged that this can best be done by raising the level of design abstraction. However there are concerns that raising the level of abstraction will impact design efficiency and quality.
This workshop will examine some of the issues involved in creating DSP systems on FPGAs, and will show how the abstraction level (and hence developer productivity) can be raised without compromising efficiency and quality. The workshop will discuss design flows and techniques for implementing DSP systems in FPGAs, including fixed and floating point modeling, tuning algorithms for efficient FPGA implementation, automatic HDL code generation, and closing the verification loop. Delegates will be shown practical examples of implementation flows starting from system models captured using MATLAB® and Simulink® from The MathWorks.
Registration
Please note that even delegates who do not wish to attend the full conference must register for the workshops using the DATE 'Conference Delegates Registration' page.
Please note that even delegates who do not wish to attend the full conference must register for the workshops using the DATE 'Conference Delegates Registration' page.
Sponsored Places
The MathWorks is sponsoring a limited number of places on this workshop. To apply for a complimentary place, simply complete the special application form.
The MathWorks is sponsoring a limited number of places on this workshop. To apply for a complimentary place, simply complete the special application form.
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