Half-day tutorial (sponsored by Synopsys & ARM)
Wednesday 22nd February, 08:00 - 12:00
Co-presented by Synopsys and Doulos

This tutorial delivers a practical explanation of the key technical and organizational features of the Verification Methodology Manual (VMM) for SystemVerilog. The VMM offers structured guidance and a consistent methodology for the construction of re-usable verification components and complete verification environments. VMM is applicable to the entire verification lifecycle - from block level through SoC to hardware/software co-verification.

Developed by Doulos in partnership with Synopsys and ARM, it highlights the benefits of the proposed methodology and illustrates how users can construct VMM-compliant verification environments powered by ready-to-use class libraries specified in the VMM. The discussion emphasizes measurement of verification completeness and productivity through proper use of functional coverage. This provides a quantitative basis for the verification effort and attendees will gain insight in how to establish verification as a mature engineering discipline within their organizations.

About the VMM for SystemVerilog
The VMM for SystemVerilog is a blueprint for system-on-chip (SoC) verification success. Written by Janick Bergeron and Eduard Cerny of Synopsys, and Alan Hunter and Andrew Nightingale of ARM, the book documents advanced functional verification techniques used by industry experts to validate complex SoCs. It describes how to use the industry-standard SystemVerilog language to create comprehensive verification environments using coverage-driven, constrained-random and assertion-based techniques, and specifies verification library building blocks for interoperable verification components.
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Thursday 23rd February, 9:00 - 10:45
Session 1 - (Design Language Evolution)
Presented by Doulos

The authors of this paper are also the authors of the SystemC Language Reference Manual. We offer a unique perspective on the changes made to the SystemC class library during the standardization process, on the new features added to SystemC, and on the important clarifications of intent that resulted from this process. The SystemC Language Reference Manual draws a clear line between the features that the class library is intended to provide to the user, and the features that are merely artifacts of the implementation. This information is important for both SystemC users and tooldevelopers.

For the benefit of SystemC users, we present examples of the new features added to SystemC since the first public beta release of SystemC version 2.1 in October 2004 and a description of the new features in SystemC 2.1 that have been significantly enhanced during the standardization process. We show how to use the new process handle mechanism to perform a variety of modeling tricks, how port policies can be used to permit optional ports, and how the new SystemC file headers can be used to control namespaces and therefore improve code quality. We present use cases showing the application of these features to transaction-level modeling and the modeling of re-usable IP.

For advanced users and tool developers, we discuss and illustrate the revised features for design hierarchy traversal and exception reporting. We show how some of the nonstandard SystemC classes have replaced by standard C++ classes, and show how the API for simulator control has been cleaned up. Finally, we discuss all the bad old features of SystemC that have been deprecated in the IEEE standard. For each deprecated feature we show a better way of doing things.

Thursday 23rd February, 09:15 - 10:45
Session 2 (Coverage)
Presented Doulos

The SystemVerilog language provides a rich set of features for dynamic control and parameterization of the constraints applied to a constrained-random stimulus generator. It also offers excellent facilities for gathering and inspecting functional coverage information. This paper examines how stimulus constraints can be modified dynamically using functional coverage data, with the aim of reducing simulation runtime needed to meet planned functional coverage goals.

In addition to traditional Boolean constraints, SystemVerilog offers programmable weighted distribution using its dist constraint, programmable weighted choice of procedural actions (randcase), and an innovative mechanism that creates random streams of transactions conforming to a user-defined grammar specified by BNF-like syntax (randsequence). In each of these constructs, weight values used to influence the random generator's choices can be modified dynamically. The language also provides for collection of functional coverage statistics (covergroup, coverpoint) and allows the cumulative coverage data to be inspected at any time during simulation. These features can be combined to implement constrained-random stimulus whose statistics are adjusted automatically during simulation.

In most situations it is non-trivial to determine appropriate constraint weightings that will drive simulation towards optimal functional coverage, and many writers and practitioners have recommended that it should not be attempted. However, the potential productivity gains from such automation are very desirable, and SystemVerilog's coverage and randomization constructs offer interesting new opportunities to revisit the idea. We identify situations where this approach is useful, and suggest some techniques that help to make it practicable.

We conclude that coverage-driven constraint can be straightforward to implement if appropriate language features are exploited, and that it can contribute usefully to productivity in some aspects of verification activity.