San Jose, February 19 - 21, 2008
Join Doulos at DVCon and tap in to our industry leading technical expertise. Visit us at booth 501 and learn from a Doulos expert in the following tutorials:
- Tutorial 1; Tuesday 19th February, 8.30 - 12 pm
The Open Verification Methodology (OVM): Opening the Door to Verification Productivity and Interoperability
- Tutorial 5; Tuesday 19th February, 1pm - 4pm
OSCI TLM-2 in 2008: A Leap Forward for Transaction-Level Modeling Standards
- Panel; Thursday, February 21, 12:00pm-1:15pm
A Firsthand Look at the Open Verification Methodology (OVM) for SystemVerilog
What's happening at booth 501?
Book an OVM Migration Consultation at the booth, check out our world leading SystemC training credentials and get an independent perspective on the leading verification methodologies. It's a great opportunity to meet the Doulos team and discover for yourself why we've become the essential choice for design and verification training for more than 700 companies across over 35 countries. We look forward to seeing you there!North American SystemC Users Meeting (NASCUG)
Tuesday February 19th, 8.30am - 1pm
Pine Room
Doulos is pleased to sponsor this key event for SystemC users in North America.
NASCUG provides a format for users to learn, interact and discuss techniques of design, modeling and verification using SystemC. Topics include:Architectural modeling
Transaction-level modeling
Hardware/software co-design
Verification techniques using SystemC
Register here >>
Pine Room
Doulos is pleased to sponsor this key event for SystemC users in North America.
NASCUG provides a format for users to learn, interact and discuss techniques of design, modeling and verification using SystemC. Topics include:
The Open Verification Methodology (OVM): Opening the Door to Verification Productivity and Interoperability
(DVCon Tutorial 1)
Tuesday February 19th, 8:30am-12:00
Oak Ballroom
Presenters:
The Open Verification Methodology (OVM) is a joint-development effort between Mentor Graphics Corp. and Cadence Design Systems to provide a SystemVerilog class library, examples, development guidelines and other collateral that incorporates many years of verification experience from both companies to assist users in developing modular, reusable, transaction-level coverage-driven testbenches. This in-depth half-day tutorial will introduce the audience to the OVM class library and show how it may be used to develop modular, coverage-driven testbenches and verification components.
Register here >>
Oak Ballroom
Presenters:
- Tom Fitzpatrick - Mentor Graphics Corp.
- Stuart Swan - Cadence Design Systems, Inc.
- John Aynsley - Doulos
The Open Verification Methodology (OVM) is a joint-development effort between Mentor Graphics Corp. and Cadence Design Systems to provide a SystemVerilog class library, examples, development guidelines and other collateral that incorporates many years of verification experience from both companies to assist users in developing modular, reusable, transaction-level coverage-driven testbenches. This in-depth half-day tutorial will introduce the audience to the OVM class library and show how it may be used to develop modular, coverage-driven testbenches and verification components.
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OSCI TLM-2 in 2008: A Leap Forward for Transaction-Level Modeling Standards
(DVCon Tutorial 5)
Tuesday February 19th, 1:30pm - 5pm
Pine Ballroom
Presenters:
Transaction level modeling (TLM) continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. The December 2007 release of the TLM2.0-Draft-2 standard from the OSCI TLM Working Group marks the culmination of several years of intensive work, and is a significant step toward making interoperable transaction level modeling a reality. This tutorial will present the details of the latest OSCI TLM2 standard. TLM2 explicitly addresses the interoperability of memory-mapped bus models at the transaction level, as well as providing a foundation and framework for the transaction level modeling of other protocols. An introduction to the concepts and the intent of the new TLM2 standard, including a brief introduction to transaction level modeling in SystemC, and a review of how TLM2 fits with the OSCI TLM1 standard. How the core TLM2 interfaces allow you to write models using the untimed, loosely-timed and approximately-timed coding styles, and how to build models that combine these approaches. How to exploit temporal decoupling at the loosely-timed level to maximize simulation speed, and how to take advantage of the new direct memory interface and debug transport interface. How the TLM2 generic payload provides off-the-shelf support for creating abstract memory-mapped bus models, how it can be extended to model specific busses and protocols, and, most importantly, how the two kinds of model can interoperate. How the generic payload extension mechanism can be used to add further attributes to a transactions in a way that does not break interoperability and minimizes the cost of building protocol bridges.
Register here >>
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Pine Ballroom
Presenters:
- John Aynsley - Doulos
- Trevor Wieman - Intel Corp
- Laurent Maillet-Contoz - ST Microelectronics
- James Aldis - Texas Instruments
Transaction level modeling (TLM) continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. The December 2007 release of the TLM2.0-Draft-2 standard from the OSCI TLM Working Group marks the culmination of several years of intensive work, and is a significant step toward making interoperable transaction level modeling a reality. This tutorial will present the details of the latest OSCI TLM2 standard. TLM2 explicitly addresses the interoperability of memory-mapped bus models at the transaction level, as well as providing a foundation and framework for the transaction level modeling of other protocols. An introduction to the concepts and the intent of the new TLM2 standard, including a brief introduction to transaction level modeling in SystemC, and a review of how TLM2 fits with the OSCI TLM1 standard. How the core TLM2 interfaces allow you to write models using the untimed, loosely-timed and approximately-timed coding styles, and how to build models that combine these approaches. How to exploit temporal decoupling at the loosely-timed level to maximize simulation speed, and how to take advantage of the new direct memory interface and debug transport interface. How the TLM2 generic payload provides off-the-shelf support for creating abstract memory-mapped bus models, how it can be extended to model specific busses and protocols, and, most importantly, how the two kinds of model can interoperate. How the generic payload extension mechanism can be used to add further attributes to a transactions in a way that does not break interoperability and minimizes the cost of building protocol bridges.
Register here >>
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A Firsthand Look at the Open Verification Methodology (OVM) for SystemVerilog
(DVCon Panel Session)
Thursday, February 21, 2008 12:00pm-1:15pm
Sierra Ballroom
Panelists:
Sierra Ballroom
Panelists:
- Dennis Brophy - Mentor Graphics Corp.
- Stan Krolikowski - Cadence Design Systems, Inc.
- Sasan Iman - SiMantis
- John Aynsley - Doulos
- Suhas Belgal - Magnum Semiconductor
This lunch panel at DVCon is one that attendees won't want to miss at DVCon 2008. The panel will include an open discussion and a firsthand look at the industry's new and exciting Open Verification Methodology (OVM). It will be technical in nature and feature technologists from both Cadence and Mentor Graphics, who have contributed both technology and resources to develop the foundation of the methodology and class libraries. The panel will also feature several early users currently building verification environments and verification IP that are taking advantage of the many benefits of the only simulator-independent, open classbased SystemVerilog methodology.
Panelists will share experiences with OVM and go deeper into the various advantages such as advanced object-orient, coveragedriven verification environment development. They will also share with the audience how the methodology supports a unique mix of RTL and transaction-level modeling and verification that scales, and how users can easily integrate these features into what they are using today. The panel will be open in nature and encourage audience participation.
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