Tuesday 5th June, 11:00 - 12:30
Presented by Doulos & CoWare
Lunch included
Room 27B, Convention Center

This Workshop will discuss standards for Transaction-Level Modeling in SystemC, in particular the new OSCI TLM2 standard.

The successful adoption of Transaction Level Modeling depends on acheiving interoperability between models from multiple sources at multiple abstraction levels. This means the ability to support models of common on-chip busses at the Programmers View (PV) level, and to annotate timing on to those models at the so-called Programmers View with Timing (PVT) level.

Addressing the challenges of interoperability at these modeling levels has been the focus of the OSCI TLM Working Group over the past year, and this effort resulted in the first release of 'TLM2' for public review in December 2006.

This workshop will present an overview of the TLM2 kit, including examples showing you how TLM2 can be used to write interoperable models at the PV and PVT levels, and will offer guidelines for successful TLM modeling. You will be shown how to use the new generic payload structures and timing annotation mechanisms in the TLM2 kit for modeling at the PV and PVT levels, and will also be shown CoWare's approach to modeling peripherals in SystemC at mixed timing abstraction levels.