Thursday 7th June, 11:00 - 1:00pm
Presented by Doulos & Synopsys
Lunch included
Room 27B, Convention Center

The Verification Methodology Manual for SystemVerilog (VMM), introduced in 2005, has rapidly become established as the de facto standard verification methodology for SystemVerilog. Synopsys recently announced its Next Generation VMM Solution, including a collection of VMM Applications. This workshop will focus on VMM Applications and demonstrate how early verification productivity can be maximized using these powerful, pre-built functions in a VMM-compliant testbench.

After a brief review of the key features of the VMM methodology, you will be shown how to apply the new VMM Applications such as the Register Abstraction Layer for flexible ready-to-use verification of device registers, new applications for creating flexible results-checking scoreboards and hierarchical verification environments plus advances in memory allocation management and in links to hardware assisted verification.