Thursday 7th June, 11:00 - 1:00pm
Presented by Doulos Certified Training Partner ALSE & The MathWorks
Lunch included
Room 27A, Convention Center

As FPGAs are becoming more widely used, two distinct challenges are emerging. Firstly, designs are becoming harder to implement due to increased silicon and system complexity. Secondly new groups of users are emerging who want to use FPGAs, but lack HDL programming skills. These two very different user communities are looking for news ways to design DSP systems on FPGAs.

Both communities are looking at increasing engineering productivity, and it is widely acknowledged that this can best be done by raising the level of design abstraction. However there are concerns that raising the level of abstraction will impact design efficiency and quality.

This workshop will examine some of the issues involved in creating DSP systems on FPGAs, and will show how the abstraction level (and hence developer productivity) can be raised without compromising efficiency and quality. The workshop will discuss design flows and techniques for implementing DSP systems in FPGAs, including fixed and floating point modeling, tuning algorithms for efficient FPGA implementation, automatic HDL code generation, and closing the verification loop. Delegates will be shown practical examples of implementation flows starting from system models captured using MATLAB® and Simulink® from The MathWorks.