Tuesday 7th March, 11:30 - 13:00
Presented by Doulos & Mentor Graphics, endorsed by ARM
Lunch 13:00 - 13:30
€50

This tutorial shows how you can use SystemVerilog Assertions (SVA) in the verification of standard bus protocols, using ARM's AXI as an example. You will learn about the assertion language built in to SystemVerilog, with practical examples of constructing assertion-based checkers for part of the AXI protocol. We show how you can make your assertions suitable for use in the vendor's formal verification tools as well as using them in simulation, and you will see a demonstration of a set of AXI assertions being used both in simulation and in the vendor's tools.

Registration
Please note that even delegates who do not wish to attend the full conference must register for the workshops using the DATE 'Conference Delegates Registration' page.

Sponsored Places
Mentor Graphics is sponsoring a limited number of places on this workshop. On-line application has now closed. To apply, please visit the Mentor Graphics booth during exhibition hours.