Wednesday 8th March, 11:00 - 12:30
Presented by Doulos & Mentor Graphics
Lunch 12:30 - 13:00
€50

The last few years have seen a proliferation of languages for hardware design, verification, and systems modelling, all staking a claim to become industry standards. EDA tool vendors now support multi-language tool environments, in which multiple design, verification and modelling languages can interoperate in a relatively seamless and trouble-free manner. This workshop will clarify the roles of several such languages; VHDL, PSL, Verilog and SystemVerilog, C++ and SystemC. Mentor Graphics will then demonstrate how these languages are integrated within their QuestaSim tool to enable a productive verification environment.

Registration
Please note that even delegates who do not wish to attend the full conference must register for the workshops using the DATE 'Conference Delegates Registration' page.

Sponsored Places
Mentor Graphics is sponsoring a limited number of places on this workshop. On-line application has now closed. If you still wish to apply, please visit the Mentor Graphics booth during exhibition hours.