Wednesday 8th March, 13:00 - 14:30
Presented by Doulos & Synopsys, endorsed by ARM
Lunch 12:30 - 13:00
€50

This workshop delivers a practical explanation of the key technical and organisational features of the Verification Methodology Manual (VMM) for SystemVerilog. The VMM offers structured guidance and a consistent methodology for the construction of re-usable verification components and complete verification environments. VMM is applicable to the entire verification lifecycle - from block level through SoC to hardware/software co-verification. Synopsys will then demonstrate how users can construct VMM-compliant verification environments using the ready-to-use class libraries specified in the VMM.

Registration
Please note that even delegates who do not wish to attend the full conference must register for the workshops using the DATE 'Conference Delegates Registration' page.

Sponsored Places
Synopsys is sponsoring a limited number of places on this workshop. On-line application has now closed. If you still wish to apply, please visit the Synopsys booth during exhibition hours.