Exploiting Processor Cores
in FPGA Designs - Large and Small
Thursday 9th March, 11:00 - 12:30
Presented by ALSE in association with Altera
Lunch 12:30 - 13:00
€50
Presented by ALSE in association with Altera
Lunch 12:30 - 13:00
€50
This Workshop will present the state-of-the-art in System-on-a-Programmable-Chip (SoPC) design with a number of very practical examples using Altera devices. It will be shown how SoPC can help guard against processor and ASSP obsolescence, and can gracefully replace first-generation micro-controllers while offering some unique advantages. It will be shown that embedding a processor in a small programmable device is easy and can make good sense. At the other end of the spectrum, high-end applications will be demonstrated, including Ethernet connectivity, Voice-over-IP, real-time Video processing and accelerated Digital Signal Processing, thus showing that SoPC is also suitable in applications traditionally reserved for ASICs.
Registration
Please note that even delegates who do not wish to attend the full conference must register for the workshops using the DATE 'Conference Delegates Registration' page.
Please note that even delegates who do not wish to attend the full conference must register for the workshops using the DATE 'Conference Delegates Registration' page.
Sponsored Places
Altera are sponsoring a limited number of places on this workshop. Applications for a sponsored place should be received by Monday 6th March. Applicants will be notified the next day whether their application has been successful. Notification will be issued by Doulos but places will be awarded at the discretion of Altera.
Altera are sponsoring a limited number of places on this workshop. Applications for a sponsored place should be received by Monday 6th March. Applicants will be notified the next day whether their application has been successful. Notification will be issued by Doulos but places will be awarded at the discretion of Altera.
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