.jpg){kind=logo}
Adopting a Plan-to-Closure Methodology across Design Teams and Verification Teams
Tuesday 17th April, 13:30 - 15:00
Presented by Doulos & Cadence
Lunch 13:00 - 13:30
€50
Presented by Doulos & Cadence
Lunch 13:00 - 13:30
€50
This workshop will cover the principles of a Plan-to-Closure methodology, from creating an executable verification plan to block, chip and system-level verification closure. The Plan-to-Closure Methodology is applicable to e, SystemVerilog, and mixed-language environments.
Throughout the workshop, the plan-to-closure approach will be demonstrated using a SystemVerilog coding style that combines modules for capturing structure with classes for capturing transaction attributes. You will be shown methodology guidelines and code examples. Topics covered will include how to capture an executable feature-based verification plan that can be leveraged to predictably manage a highly automated coverage-driven verification testbench.
The workshop will also show you how to best leverage SystemVerilog language features to support assertions, coverage-driven, constrained-random test generation, and how testbench automation fits into a complete verification flow, including formal analysis, transaction-based acceleration, and HW/SW co-verification.
After attending this workshop you will understand the main principles of a Plan-to-Closure approach to verification and you will be aware of clear guidelines for developing an executable verification plan and building a reusable verification environment.
Throughout the workshop, the plan-to-closure approach will be demonstrated using a SystemVerilog coding style that combines modules for capturing structure with classes for capturing transaction attributes. You will be shown methodology guidelines and code examples. Topics covered will include how to capture an executable feature-based verification plan that can be leveraged to predictably manage a highly automated coverage-driven verification testbench.
The workshop will also show you how to best leverage SystemVerilog language features to support assertions, coverage-driven, constrained-random test generation, and how testbench automation fits into a complete verification flow, including formal analysis, transaction-based acceleration, and HW/SW co-verification.
After attending this workshop you will understand the main principles of a Plan-to-Closure approach to verification and you will be aware of clear guidelines for developing an executable verification plan and building a reusable verification environment.
 |
 |
