Wednesday 18th April, 13:00 - 14:30
Presented by Doulos & Synopsys
Lunch 12:30 - 13:00
€50

The Verification Methodology Manual for SystemVerilog (VMM) and its associated class library, introduced in 2005, has rapidly become established as a key driver of verification practice using SystemVerilog. More recently Synopsys announced its 'Next Generation VMM Solution' incorporating VMM Planning, Applications and Automation. This workshop will focus on VMM Applications and demonstrate how early verification productivity can be maximised using these powerful, pre-built applications in a VMM-compliant testbench.

The workshop will show you how to build the complex general-purpose parts of your testbench as quickly and efficiently as possible, so that you can concentrate on completing your verification task instead of wasting valuable project time on building infrastructure.

After a brief review of the key features of the VMM methodology, you will be shown how to apply the new VMM Applications such as the Register Abstraction Layer for flexible ready-to-use verification of device registers, new applications for creating flexible results-checking scoreboards and hierarchical verification environments plus advances in memory allocation management and in links to hardware assisted verification.