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Using SystemC and SystemVerilog together in an Advanced Verification Methodology
Thursday 19th April, 11:00 - 12:30
Presented by Doulos & Mentor Graphics
Lunch 12:30 - 13:00
€50
Presented by Doulos & Mentor Graphics
Lunch 12:30 - 13:00
€50
This Workshop will discuss functional verification methodology using Mentor's Advanced Verification Methodology as an example of how SystemC and SystemVerilog can be combined within a single coherent environment to support assertions, functional coverage, stimulus generation, and transaction-level modeling.
The workshop will show you how to refine a reference model written in SystemC through a transaction-level model in SystemVerilog to an HDL implementation, and how they can all execute within an AVM-compliant SystemVerilog testbench. You will also be shown how to pass transactions between the two languages, and how to build a verification environment that can be re-used within the refinement process from algorithmic SystemC to RTL.
The workshop will also show how verification techniques such as sequence generation, synchronization between testbench components, and error injection can be implemented within the AVM framework.
The workshop will show you how to refine a reference model written in SystemC through a transaction-level model in SystemVerilog to an HDL implementation, and how they can all execute within an AVM-compliant SystemVerilog testbench. You will also be shown how to pass transactions between the two languages, and how to build a verification environment that can be re-used within the refinement process from algorithmic SystemC to RTL.
The workshop will also show how verification techniques such as sequence generation, synchronization between testbench components, and error injection can be implemented within the AVM framework.
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