San Jose, February 21-23, 2007
This year at DVCon we are once again giving you the opportunity to tap into our industry leading technical expertise. Join us for...
And don't forget to visit us at booth 204. It's a great opportunity to discover for yourself why Doulos has become the essential choice for design and verification training for more than 600 companies across over 30 countries.
Check out the latest industry leading Doulos SystemVerilog and SystemC training materials. Don't miss your opportunity to go home with a copy of the sought-after Doulos Golden Reference Guides!
- North American SystemC Users Meeting (NASCUG)
- Practical Applications of Mentor’s Advanced Verification Methodology (AVM)
- SystemC Transaction Level Modeling Standards and Methodology Guidelines
- SystemVerilog for Design
And don't forget to visit us at booth 204. It's a great opportunity to discover for yourself why Doulos has become the essential choice for design and verification training for more than 600 companies across over 30 countries.
Check out the latest industry leading Doulos SystemVerilog and SystemC training materials. Don't miss your opportunity to go home with a copy of the sought-after Doulos Golden Reference Guides!
North American SystemC Users Meeting (NASCUG)
Wednesday 21st February, 08:30 - 13:00
Donner Ballroom
Doulos is pleased to sponsor this key event for SystemC users in North America.
Back to topDonner Ballroom
Doulos is pleased to sponsor this key event for SystemC users in North America.
Practical Applications of Mentor’s Advanced Verification Methodology (AVM)
(DVCon Tutorial 2)
Wednesday 21st February, 09:00 - 12:30
Oak Ballroom
Presenters:
Tom Fitzpatrick - Mentor Graphics
Harry Foster - Mentor Graphics
Ambar Sarkar - Paradigm Works
John Aynsley - Doulos
This in-depth, half-day tutorial covers using the Mentor Graphics Advanced Verification Methodology (AVM) to develop testbenches for real-world applications. The tutorial walks-through a detailed example of writing a testbench for a moderately complex design, the overall architecture, construction of individual verification components, and infrastructure to allow new scenarios to be generated with minimum additional coding.
While many engineers understand the concepts of new verification techniques, they may be unsure of how best to apply them to their particular project. Mentor’s AVM was developed explicitly to help verification teams get past this “blank page” phase of the project by providing a library of modular, reusable transaction-level verification components to efficiently create transaction-level testbenches for today’s advanced technologies: constrained-random stimulus, functional coverage, and assertions.
The tutorial begins with an overview of Transaction-Level Modeling, the AVM library, AVM components usage, the planning and analysis required to determine the optimal architecture for the verification of a router design (developed by Paradigm Works). Key aspects of the testbench: stimulus generation, assertions for functional coverage, and scoreboarding are discussed, plus a demonstration encapsulating the testbench for reusability and customization.
The next section covers writing effective assertions for simulation and formal verification, using assertions to gather transaction-level information, and how the AVM communicates information between modules and classes throughout the testbench.
The tutorial concludes with the AVM development process, the collaboration between Mentor Graphics, its partners, and customers. This discussion includes Dr. Sarkar on an overview of the SytemVerilog Frameworks, and Mr. Ansley on coverage-based methodology.
Back to top
Oak Ballroom
Presenters:
Tom Fitzpatrick - Mentor Graphics
Harry Foster - Mentor Graphics
Ambar Sarkar - Paradigm Works
John Aynsley - Doulos
This in-depth, half-day tutorial covers using the Mentor Graphics Advanced Verification Methodology (AVM) to develop testbenches for real-world applications. The tutorial walks-through a detailed example of writing a testbench for a moderately complex design, the overall architecture, construction of individual verification components, and infrastructure to allow new scenarios to be generated with minimum additional coding.
While many engineers understand the concepts of new verification techniques, they may be unsure of how best to apply them to their particular project. Mentor’s AVM was developed explicitly to help verification teams get past this “blank page” phase of the project by providing a library of modular, reusable transaction-level verification components to efficiently create transaction-level testbenches for today’s advanced technologies: constrained-random stimulus, functional coverage, and assertions.
The tutorial begins with an overview of Transaction-Level Modeling, the AVM library, AVM components usage, the planning and analysis required to determine the optimal architecture for the verification of a router design (developed by Paradigm Works). Key aspects of the testbench: stimulus generation, assertions for functional coverage, and scoreboarding are discussed, plus a demonstration encapsulating the testbench for reusability and customization.
The next section covers writing effective assertions for simulation and formal verification, using assertions to gather transaction-level information, and how the AVM communicates information between modules and classes throughout the testbench.
The tutorial concludes with the AVM development process, the collaboration between Mentor Graphics, its partners, and customers. This discussion includes Dr. Sarkar on an overview of the SytemVerilog Frameworks, and Mr. Ansley on coverage-based methodology.
SystemC Transaction Level Modeling Standards and Methodology Guidelines
(DVCon Tutorial 5)
Wednesday 21st February, 13:30 - 17:00
Fire Ballroom
Presenters:
John Aynsley - Doulos
Stuart Swan - Cadence Design Systems
Trevor Wieman - Intel
Ryan Bedwell - Freescale Semiconductor
Transaction Level Modeling (TLM) is important for architectural exploration and performance modeling, for building virtual prototypes of hardware platforms for early software development, and for writing testbenches for hardware verification. The first release "TLM1" of the OSCI TLM standard in 2005 provided a standard set of interfaces that permit plug-and-play between transaction-level components at the transport layer, particularly useful for untimed modeling in a verification environment.
The successful adoption of TLM depends on the interoperability of models from multiple sources at multiple abstraction levels. Right now, this means the ability to support models of common on-chip busses at the Programmers View (PV) level, to annotate timing onto those models (PVT), and to support Cycle Accurate (CA) modeling. Addressing the challenges of interoperability at these modeling levels has been the focus of the OSCI TLM Working Group over the past year, and this effort resulted in the first release of "TLM2" for public review in late 2006.
After a brief introduction to SystemC and TLM, this tutorial will present an in-depth discussion of the many technical issues raised and addressed by TLM2, will provide examples showing how TLM2 can be used to write interoperable models at the PV and PVT levels, and will offer guidelines for successful TLM modeling.
Agenda:
Back to top
Fire Ballroom
Presenters:
John Aynsley - Doulos
Stuart Swan - Cadence Design Systems
Trevor Wieman - Intel
Ryan Bedwell - Freescale Semiconductor
Transaction Level Modeling (TLM) is important for architectural exploration and performance modeling, for building virtual prototypes of hardware platforms for early software development, and for writing testbenches for hardware verification. The first release "TLM1" of the OSCI TLM standard in 2005 provided a standard set of interfaces that permit plug-and-play between transaction-level components at the transport layer, particularly useful for untimed modeling in a verification environment.
The successful adoption of TLM depends on the interoperability of models from multiple sources at multiple abstraction levels. Right now, this means the ability to support models of common on-chip busses at the Programmers View (PV) level, to annotate timing onto those models (PVT), and to support Cycle Accurate (CA) modeling. Addressing the challenges of interoperability at these modeling levels has been the focus of the OSCI TLM Working Group over the past year, and this effort resulted in the first release of "TLM2" for public review in late 2006.
After a brief introduction to SystemC and TLM, this tutorial will present an in-depth discussion of the many technical issues raised and addressed by TLM2, will provide examples showing how TLM2 can be used to write interoperable models at the PV and PVT levels, and will offer guidelines for successful TLM modeling.
Agenda:
- A brief intro to SystemC and TLM plus the role of TLM today
- A review of OSCI TLM1 standard, and how to take advantage of TLM1 principles in practical modeling situations
- Discussion of the implementation of TLM2 using worked examples
- A glimpse at the new features of TLM2 for 2007
- A presentation from a TLM user on adopting TLM2
SystemVerilog for Design
(DVCon Thursday Session 1)
Thursday 22nd February, 10:30 - 12:00
Donner Ballroom
Session Chair:
Cliff Cummings - Sunburst Design
Presenters:
Stefan Sandström - Axis Communications
Bill Dittenhofer - AMI Semiconductor
Jonathan Bromley - Doulos
Agenda:
Back to topDonner Ballroom
Session Chair:
Cliff Cummings - Sunburst Design
Presenters:
Stefan Sandström - Axis Communications
Bill Dittenhofer - AMI Semiconductor
Jonathan Bromley - Doulos
Agenda:
- Designing a System-on-Chip with SystemVerilog In the Real World
- Through the Looking Glass - A User's Perspective on SystemVerilog, SystemC
- Towards a Practical Design Methodology with SystemVerilog Interfaces and Modports
