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Doulos extends on-line learning program in May

Doulos are pleased to announce two new webinars in May as part of their on-going commitment to providing high value, cutting edge KnowHow resources:

Friday May 4: Sythesis-Friendly SystemVerilog »

Friday May 11: First Steps in UVM »

Registration and attendence is free of charge.

Find out about the current on-line training schedule and register »

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Page last updated 10 June 2013.

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Resources

NEW Resources!
Using TCL to implement an HDL design in a Xilinx FPGA. More>>

NEW TLM-2.0 Base Protocol Checker. More>>

Updated: "Getting Started with TLM-2.0" More>>

VHDL-200x - find out about the latest revision of VHDL. More>>