At Last, One Functional Verification Methodology for Everyone!
Adding to the broadest verification training program available already covering methodology standards VMM and OVM, Doulos announces support for the single Universal Verification Methodology recently released by Accellera.
Doulos has been pleased to work in close co-operation with its partners in the EDA industry to ensure early availability of this key training program.
Available for delivery worldwide from July, this 3 day class enables verification teams to gear up for the fullest productivity in verification utilising SystemVerilog and UVM with fully independent specialist training from Doulos subject matter experts.
Check out more details here
Doulos has also released a summary of UVM supported by introductory free technical resources on its website; check them out here
Doulos will be publishing the UVM Golden Reference Guide later in 2010. You can register your interest to receive notification when it becomes available. (Please note this has now expired).
Doulos is proud to announce the extention of its relationship with Xilinx by becoming the Authorized Training Provider for Northern California.
The powerful combination of focused, up-to-date technology training created by Xilinx and best-in-class language and methodology training from Doulos will provide new possibilities for design and verification engineers to get the best performance from their designs and their own efforts. Doulos provides a one stop shop for essential knowledge and skills covering detailed technology facts and techniques to systems level modeling and verification methodologies across hardware and embedded software domains. The opportunities for engineering teams to improve performance through effective, integrated training programmes have never been so good.
“Doulos has an excellent track record in delivering high-quality training services to Xilinx customers, working hand-in-hand with our worldwide sales organization,” said Jason Fegley, Training Manager at Xilinx. See full press release for more details.
- C for Real-Time Developers
- Advanced C Programming
- C++ for Embedded Developers
- Advanced C++ for Embedded Systems
- Design Patterns in C++ for Embedded Systems
- Real-Time Software Design with UML 2.0
- Fundamentals of RTOS
- Developing for Embedded Linux
- Developing Linux Device Drivers
Actel's Sr. Manager, Design Solutions Marketing and Training Wendy Lockhart, comments on the partnership with Doulos, "We are happy to have Doulos as a very competent and highly qualified training and support partner for SmartFusion. It will help our customers very quickly adopt this new and exciting technology to considerably shorten their time-to-market."
Go to www.doulos.com/actel to find out more..
Paper: The quickest way to develop your ARM Cortex-M based product
Paper: Using ARM Advanced SIMD (NEON) from C with vectorizing compiler
(Please note the following links have now expired)
Doulos have a strong presence at DVCon in San Jose, February 22-25, participating in two half-day tutorials and three regular papers. Check out the details below:Tutorial - Advanced Verification Techniques Using VMM. Doug Smith of Doulos leads a great team of experts presenting an in-depth tutorial which includes real-world examples of best-practice VMM usage. Attendees will get the know-how needed to begin using the latest features in their own projects.
Tutorial 1 (Session 20); Monday February 22, 1.30 - 5.00pm
Tutorial - The OSCI TLM-2.0 Standard and Synthesis Subset. John Aynsley Doulos CTO, Michael Meredith of Forte Design Systems and Michael McNamara of Cadence explore the lessons learned from the practical adoption of the TLM-2.0 standard, the resulting resurgence of SystemC synthesis, and the synergy between the two
Tutorial 2 (Session 21); Monday February 22, 1:30 - 5:00pm
Paper - SystemVerilog Meets C++: Re-use of Existing C/C++ Models Just Got Easier.
Presenter: John Aynsley
Session 4.1; Wednesday February 24, 11.00am - 12.30pm
Paper - Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions
Presenter: Doug Smith
Session 11.2; Thursday February 25, 1.30 - 3.00pm
Paper - Functional Coverage - without SystemVerilog!
Presenter: Doug Smith
Session 13.1; Thursday February 25, 1.30 - 3.00pm
Conference Home Page
Date: Thursday December 3rd
Time: 11:00 am - 12:00 pm PDT USA and 3:00 pm - 4:00 pm CEST
- ARM Embedded specialists
- Verification specialists
- FPGA specialists
Click here for more details >>