Doulos announces new Expert VerilogŪ course, 24 September 2001.
Doulos have extended their range of HDL courses to include Expert VerilogŪ. The natural successor to our industry standard Comprehensive Verilog course, it is split into two modules, Expert VerilogŪ Design and Expert VerilogŪ Verification. It focuses on language and synthesis issues, design re-use, test benches and 'hot' techniques for verification.
- Expert VerilogŪ Design (2 days) for design engineers wishing to deepen their knowledge of both RTL and behavioural synthesis using Verilog, and to improve their Verilog coding style with design re-use in mind.
- Expert VerilogŪ Verification (3 days) for design engineers and verification engineers involved in Verilog test bench development, or behavioural modelling, for the purpose of functional verification.
This course is suitable for engineers who have already attended our Comprehensive VerilogŪ course or have extensive VerilogŪ project experience, and need to increase their productivity by enhancing their coding and application skills. As with all Doulos courses, 50% of course time will be spent in practical workshops, enabling engineers to apply their new skills using the VerilogŪ tools of their choice; click here for the full course description.
The first public Expert VerilogŪ course will be running at the Marriot Hotel in Swindon between the 19 - 23 November 2001. Onsite courses are available worldwide now, so call the Sales Team on +44 (0) 1425 471223 or email us for pricing and scheduling information.