RapidGain™ VHDL Using Xilinx
Duration - 1 day
View dates and locations Auf Deutsch
RapidGain™ VHDL Using Xilinx is unique in offering delegates experience of the whole FPGA design flow, from VHDL coding and simulation through to downloading a design to a real device, all in a single day. Tightly focused and practical, this one-day hands-on training event will show new and prospective users how to get started with VHDL and Xilinx FPGAs.
Delegates will rapidly gain an understanding of the tools and processes involved in creating an FPGA design, achieving significant initial productivity gains. You will:
RapidGain™ VHDL Using Xilinx is not available for in-house delivery.
Delegates will rapidly gain an understanding of the tools and processes involved in creating an FPGA design, achieving significant initial productivity gains. You will:
- Understand the basic structure of Xilinx FPGAs
- See how VHDL is used to capture and simulate your FPGA design
- Implement a design, step by step, in the Xilinx ISE environment
- Download and test your design on a Spartan 3E development board
RapidGain™ VHDL Using Xilinx is not available for in-house delivery.
Who should attend?
- Digital designers thinking about making the first moves to VHDL and FPGA design
- Managers who want to understand more about the process of creating FPGA designs and VHDL
- Analogue or Systems designers who work with digital design teams
Prerequisites
No prior experience of VHDL or Xilinx FPGAs and software is needed. You should have a basic understanding of digital logic design, and be computer-literate.Structure and content
Getting Started with VHDL
What is an FPGA? • What is VHDL? • Tools for FPGA design • How does VHDL affect my design style? • Design flow • Design entity • Ports • Signals • STD_LOGIC • Signal assignment • Processes • Hierarchy • Testbenches • Simulation with ModelSimLAB: Simulating a binary counter, using ModelSim
Using the Xilinx ISE Software
Xilinx ISE software • Creating a project • Constraints for timing and pins • Implementing a design using the ISE software • Gate-level simulationLAB: Implementing counter using ISE, and programming a development board
Writing VHDL for Synthesis
Summary of VHDL constructs and their synthesis • Creating finite state machines Synchronous and Asynchronous controls • The NUMERIC_STD packageLAB: Modifying the counter, re-implement and re-program the FPGA
Where do I go from here?
Summary and conclusions • Doulos VHDL, and FPGA training roadmapThis course is available now for team-based training at or near to your location. To find out more:
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