Advanced FPGA Implementation

Advanced Level - 2 days

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Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE™ 9.1i tool suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover Synplicity's Synplify and the Xilinx XST tools.The lecture material in this course covers the ISE software 9.1i tools and the Virtex™-4 FPGAs.

This course uses materials developed by Xilinx for delivery by Doulos, the Authorised Training Provider for Xilinx in the UK and Ireland.

Who should attend?

Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilisation and productivity

Pre-requisites

Prior attendance of Fundamentals of FPGA Design
Prior attendance of Designing for Performance
Intermediate knowledge of VHDL or Verilog
At least six months' design experience with Xilinx tools and FPGAs

Software Tools

Xilinx ISE 9.1i
Synplicity Synplify
Xilinx XST

Skills gained

After completing this training, you will have the necessary skills to:

Create and edit timing constraints in the UCF file
Utilise Tcl-based scripting to implement a design
Analyse I/O interface timing and implement timing constraints and design modifications to meet System and Source Synchronous I/O interface timing
Utilise Partitions and SmartGuide™ technology to preserve timing results
Demonstrate floorplanning techniques to enhance timing
Optimise the post-place-and-route design in the FPGA Editor for more efficient in-circuit testing

Course Outline

Introduction
Lab 1: Achieving Timing Closure
Section 1: Advanced Implementation Control
Tcl Scripting
Lab 2: Tcl Scripting
UCF Editing
Lab 3: UCF
Advanced I/O Timing
Lab 4: Advanced I/O Timing
Section 2: Design Preservation
SmartCompile Design Preservation Techniques
Lab 5: SmartCompile
Floorplanning Effective Layout
Lab 6: Floorplanning
Section 3: Reduce Debug Time
FPGA Editor: Viewing and editing a routed design
Lab 7: FPGA Editor

Lab Descriptions

Note: Labs will be based on Xilinx ISE 9.1i software.

Lab 1 - Achieving Timing Closure - Create global timing constraints, read timing reports, apply path-specific constraints (multicycle and false paths), and apply advanced implementation options.
Lab 2 - Tcl Scripting - Write program commands in a Tcl script file to implement the design. Then modify program switches to obtain the greatest possible performance from the design.
Lab 3 - UCF - Write constraints directly into a UCF file to guide the performance results of implementation.
Lab 4 - Advanced I/O Timing - Compose timing constraints for I/O interface. Analyse the timing failures and determine changes to correct the timing issues. Modify the design to fix timing failures.
Lab 5 - SmartCompile - Utilise SmartGuide and Partitions to preserve timing results between design iterations.
Lab 6 - Floorplanning - Implement a design using floorlplanned constraints to enhance the timing results over a design without floorplanning.
Lab 7 - FPGA Editor - Use the FPGA Editor to view and edit a design. Analyse the contents of a CLB; add a probe; remove, place, and modify components; and analyse long nets.

Course Dates:
April 14th, 2008	s-Hertogenbosch, NL	Enquire
May 15th, 2008	Dublin, ROI	Enquire
June 5th, 2008	Bournemouth, UK	Enquire
August 7th, 2008	Bournemouth, UK	Enquire
August 19th, 2008	s-Hertogenbosch, NL	Enquire

Courses scheduled in s'Hertogenbosch are delivered by 'Arcobel', the Doulos Certified Training Provider (CTP) for the Benelux region.