Altera NIOS II SoPC
Standard Training - 3 days
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Course updated June 2011
Altera NIOS II SoPC is a 3-day course aimed at engineers who are using Altera technology to design Systems on Programmable Chip.The course covers both hardware and software aspects of the design flow and is accessible to both hardware and software engineers. This co-training approach enables successful team working on SoPC designs, in that both software and hardware engineers gain an appreciation of the requirements of each other's discipline. This ensures successful convergence in the design flow and the development of efficient architectures.
The scope of the course includes an appreciation of the hardware platform, hardware-software partitioning, hardware acceleration as well as software development and debugging. These concepts are reinforced by numerous and varied practical exercises, using the latest tools and technology, on actual hardware platforms.
Altera NIOS II SoPC is developed and maintained for Doulos by specialist partner ALSE based on source material from Altera.
Doulos and ALSE are Approved Altera Training Partners.
Who should attend?
Design engineers who wish to learn how to use Altera technology for Systems on Chip.What will you learn?
- Designing the hardware platform
- Software-hardware partitioning and cooperation
- Hardware acceleration techniques and integration
- Software development & debugging using Eclipse IDE
- The advantages of the new QSys tools and the Network On Chip technology
Pre-requisites
All participants must be computer literate and have a basic understanding of digital design. For the first day, a prior understanding of Quartus II is preferable, but not mandatory. For the third day, prior experience in C or C++ is preferable, but not mandatory.Structure and Content
Day 1
Designing a System on a Programmable Chip (SoPC)
Why and when to use SoPC • Introduction to the Nios II processors family and options • Selecting and configuring the Processor, the IPs, the available standard and specific peripherals • Introduction to the Hardware flow using SoPC Builder and Quartus II.Practical Exercise: Creating a complete SoPC from scratch, tested on the FPGA Kit.
Validating the Hardware Platform by HDL (co)simulation
Creating the simulation environment • Modeling the Peripherals and the UART • Using ModelSim to simulate the complete SoPC system.Practical Exercise: RTL Simulation with ModelSim of the SoPC system created previously.
The Avalon Switch Fabric - Custom Peripherals & Custom Instructions
The Avalon bus and interconnection system • Miscellaneous kinds of peripheral ports and transfer modes • Master with and w/o wait state • Slave mode and wait states • Streaming mode • Multi-Master and multi-CPU systems • Datapath widths and Data & Address alignment issues • Generating the Switch Fabric • Adding custom peripherals.Practical Exercise : Creation, integration and test of a custom peripheral (PWM controller).
Introducing QSys
Concepts • Advantages • Drawbacks • Limitations • Roadmap.Practical Exercise: creating a complete system with Qsys • Comparing with SoPC Builder.
Day 2
Common Embedded Periperals
SystemID • JTag UART • On-chip memory • PIO • Timer • Nios • JTag debug • Custom Peripheral.Practical Exercise: Design & use of a simple Custom Peripheral (PWM in VHDL).
Custom Instructions and Hardware Acceleration
Motivation and concept of Hardware Acceleration • Implementing and integration in the Hardware and software design flow • Different kinds of Custom Instructions • Practical examples.Practical Exercise: Accelerating a CRC calculation using a Custom Instruction.
Multi-Masters systems and Direct Memory Access (DMA) Controllers
Limitation of Traditional architectures • Using Avalon simultaneous multi-master capabilities to optimize the performance • Master/Slave DMA transfers • Streaming mode • Master arbitration scheme • Accelerating software execution.Practical Exercise: Further acceleration using a DMA controller and a custom peripheral.
Working with the Development boards
Configuring and assigning the I/Os • Understanding the clock domains • Downloading the FPGA and loading the RAM and Flash memories contents • Typical SoPC board architecture • Tips and techniques • Restoring the factory default configuration.The NIOS II processor • The Software Development Environment
Main concepts • Software aspects • Introduction to Nios II EDS / Eclipse SBT • Creating a software project • Basic tools for compilation and debugging • Project management • Creating a C/C++ application and associated Board Support Package.Practical Exercise: Creating a Software Project from scratch • testing it on the Hardware.
Day 3
Developing Programs for Nios II: the HAL.
Introduction to the Hardware Abstraction Layer (HAL) and programming model for standard basic peripherals: system clock, alarm, time-stamp and high-resolution timers • Programming the peripherals • The role of the data cache • Handling custom peripherals.Practical Exercise: Using the HAL API to exercise PIOs and Timers.
Nios II Embedded Systems and Software Architectures
System.h • Updating the hardware configuration • Memory mapping • Stack • Heap • The linker • Mastering the boot sequence (alt_sys_init and alt_main) • Hosted vs Free-Standing, optimizing the code size • HAL and file system • Unix-style functions.Practical Exercise: Observing the HAL init phase • testing the Stack overflow protection • measuring and reducing the code footprint, moving the code location with the linker.
Interrupts
Caveats about legacy interrupts • Presenting the two Interrupts modes and hardware • Pros and Cons of the Cascadable Vectored Interrupt Controller • Using and programming the standard interrupt controller.Practical Exercise: Enhance the PWM lab to use Interrupts generated by the edge-triggered PIO.
Custom Instructions and Hardware Acceleration, C2H
Identifying the performance bottlenecks • Creating and using custom instructions • Hardware acceleration through dedicated custom hardware peripheral, with or without DMA transfers • Issues with Data cache.Practical Exercise: Simple algorithm • Optimized software implementation • Accelerating with a custom instruction • Hardware acceleration with dedicated hardware block and DMA transfers • Accelerating with C2H • Measuring and comparing Performance.
| Course Dates: | |||
|---|---|---|---|
| May 22nd, 2013 | Munich, DE | Course has started | |
| October 21st, 2013 | Munich, DE | Enquire | |
| October 28th, 2013 | Ringwood, UK | Book online | Enquire |
Looking for team-based training, or other locations?
Price on request
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