Altera Designing with Quartus II
Standard Level - 3 days
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Altera Designing with Quartus® II is a 3-day course aimed at engineers designing Altera® FPGAs, including the Cyclone® and Stratix® families. You will learn how to make best use of the latest features of the Quartus II software, including all the productivity and efficiency benefits of using TimeQuest Timing Analysis, Incremental Design and PowerPlay power analysis and optimisation.
Approximately 50% of class time is spent on practical exercises to reinforce the lectures. The exercises make use of a development board to emphasise the real-world application of the techniques learned.
Altera Designing with Quartus II is developed and maintained for Doulos by specialist partner ALSE based on source material from Altera. Doulos and ALSE are Approved Altera Training Partners.
Who should attend?
Existing users, who wish to become more productive by extending their knowledge of Quartus II and exploiting the latest features and techniques.Design engineers who are new to Quartus II, and want quickly to get fully up to speed with all the key features of Quartus II. Please see the pre-requisites below.
What will you learn?
- How to make best use of the full capability of the Quartus II software to implement your design.
- Reports and Clock Constraints, IO Constraints and Synchronous Interfaces, Source Synchronous Interfaces and Asynchronous Paths and Exceptions using TimeQuest.
- Use Incremental Compilation techniques, including creating LogicLock™ regions (Floorplanning) and Partitions to reduce compile times and more easily achieve timing closure.
- Estimating, analysing and optimising power consumption.
- Improve productivity and quality by automating the design flow using scripts.
- Functional and timing simulation using ModelSim®.
- Debugging designs using SignalTap® II and SignalProbe.
Pre-requisites
All participants must be computer literate and have a basic understanding of digital design.The main course focus is on the more advanced features of Quartus II. A basic working knowledge of Quartus II would be beneficial, but is not absolutely essential. You can obtain this from the online tutorial included with Quartus II. This is also available online at www.altera.com.
Course Content
Day 1
Introduction to Quartus II, the Altera Environment and Altera Devices
Quick introduction to the Altera offer • the Main Devices families and the Design Environment • Operating Systems supported and Roadmaps.The Quartus II Design Flow - Part I
User Interface, Environment • Design Entry Methods (HDLs & Text Editors, Megawizard, Schematics and FSM Graphical Entry, Memory Editor) • Project Management basics (Creation, File & Archive management, Device selection) • Main steps in the Design Flow from entry to compilation.Practical Exercise.
The Quartus II Design Flow - Part II
Pin assignment • Constraints and Assignment Editor • Dynamic checking • The Pin Planner • CSV Import/Export • Virtual pins • Place & Route • Fitter control • Download / target programming • JTag chains • dealing with composite chains • using JTag Indirect Programming (JIC) • JTag Server and remote use through Ethernet.Practical Exercise on FPGA board.
Advanced use of Quartus II
Version-compatible databases • Project archival • Creating and comparing Revisions • Using the RTL • Technology & FSM Viewers • Cross-probing • Intelligent Message suppression • Design Rule Checking • Optimization Advisors.Practical Exercise.
Design Flow Automation - Scripting
For improved productivity and quality, design tasks and project management can be automated and secured with command-line scripts and Tcl scripts: Project creation, file management, archival, cleanup, compilation, bitstream creation, result testing, etc...Practical Exercise on FPGA board.
Functional (RTL) and Timing (Post-layout) Simulation with ModelSim (Altera Edition)
Introduction to ModelSim AE • The steps of RTL simulation and debugging • scripting • Adapting the Testbench to the post-layout model • Generating the timing models (Vital / sdf).Practical Exercise.
Chip Planner
Concept • applications • use.Day 2
Power Estimation and Optimization
Using Powerplay • Early estimation + refined vector-based statistical estimation • Understanding the principles of power reduction at RTL and P&R, using the Power Adviser.Practical Exercise.
In-System Memory Contents Editor + In-System Sources & Probes
Discover these very useful free tools that are easy to use • Concept • Applications • How-To.Practical Exercise: Parametrization of an existing design in real time through the JTag port.
SignalTap II
Embedded Real Time Logic Analyzers to debug the design in real time • Concepts • Creating the STP file • Implementation • Applications • Preparation • Compilation • Static and dynamic configuration • Buffer types • Triggering • sampling • Data storage & analysis • The PowerUp Trigger • How-Tos • Viewing Real Time captures of State Machines.Practical Exercise: real-time debugging of an external memory interface.
SignalProbe, Logic Analyzer Interface
Take advantage of these JTag Instrumentation debugging tools that come with Quartus II at no extra cost to drive an external Logic Analyzer or to probe internal net(s) on spare I/O(s) • Incremental Compilation & LogicLock are Techniques to partition a design and achieve better results for complex or challenging designs • Application • Practical use • Top-down and bottom up flows • Preserving the performance • Using the Design Partition Planner • Virtual Pins.Practical Exercise I or Practical Exercise II.
Day 3
TimeQuest Part I: Discovering TimeQuest, new Concepts and User Interface
Introduction to the Synopsys Design Constraints format (SDC) • STA from the Graphical User Interface and from SDC files • Slack Calculations • Multi-corner Analysis • The TimeQuest STA practical flow.Practical Exercise.
TimeQuest Part II: Reports and Clock Constraints
Timing Reports • Advanced Reporting • Waveform Analysis Tcl Scripts • Custom Reports • Synopsys Design Constraints format (SDC): terminology and syntax • Constraining Base • Generated and Virtual Clocks • PLL constraints • Clock Latency • Clock Uncertainty • Metastability & Jitter analysis.Practical Exercise.
TimeQuest Part III: IO Constraints and Synchronous Interfaces
Constraining Combinatorial interfaces • IOs Minimum and Maximum Delays • use of Virtual Clocks • Pin Load and Avanced IO Timing • Reporting IO Timings.Practical Exercise.
TimeQuest Part IV: Source Synchronous Interfaces
Concepts • constraining and verifying Source-Synchronous Interfaces • Edge and Center-Aligned Schemes • SDR and DDR Schemes • SDR Complete Source Synchronous example • Reporting Source Synchronous Timings.Practical Exercise.
TimeQuest Part V: Asynchronous Paths and Exceptions
Advanced Concepts • Recovery-Removal Analysis • Asynchronous and False Paths • Clock Domains Crossing management • Clock Multiplexing • Multi-Cycles Paths • Absolute Delays • Max Skew • Time Groups.Practical Exercise.
Timing Optimization Options
Optimization options • Synthesis Options • Timing Driven Synthesis • WYSIWIG Re-synthesis • Physical synthesis • Retiming • Register duplication • Pros & Cons • Fitter Options • Design Space Explorer • Concept & use.In-System Memory Contents Editor
Concept and Use • ApplicationsAdditional Options for In-house Delivery
Designing with Quartus II is available both as a publicly scheduled course and for in-house delivery. On scheduled courses, all the topics listed above will be taught. Additional exercises and optional topics may be taught at the course leader's discretion, depending on the time available and on the interests of the delegates.For in-house delivery, there is more scope for customising the course contents. Please contact Doulos to discuss your requirements.
| Course Dates: | |||
|---|---|---|---|
| September 9th, 2013 | Munich, DE | Enquire | |
| September 18th, 2013 | Ringwood, UK | Book online | Enquire |
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