Altera Designing with
Quartus II

Standard Level - 3 days

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Altera Designing with Quartus II is a 3-day course aimed at engineers who need to design Altera devices using Quartus II effectively and proficiently.

The course covers all the techniques and know-how required to create successful designs, covering the full spectrum from simple to complex FPGA projects.

All the main features and capability of the Quartus II software are taught in depth. In addition, the know-how gained in this course covers major aspects of the design flow including floorplanning, static timing analysis, power analysis, and design flow automation.

Approximately 50% of class time is spent on practical exercises to reinforce the lectures. The exercises use a development board.

Altera Designing with Quartus II is developed and maintained for Doulos by specialist partner ALSE based on source material from Altera.

Doulos and ALSE are Approved Altera Training Partners.

Who should attend?

Design engineers who wish to design Altera programmable devices with Quartus II.

What will you learn?

How to use the basic and advanced features of the Quartus II software to implement your design
Improve productivity and quality by automating the design flow using scripts
Functional and timing simulation using ModelSim
How to specify timing constraints and perform static timing analysis
Techniques for optimizing the speed and area of your designs.
Estimating and anlyzing power consumption
Floorplanning, modular and incremental design flows
Debugging designs using SignalTap II and SignalProbe

Pre-requisites

All participants must be computer literate and have a basic understanding of digital design.

Structure and Content

Day 1

Quartus II and the Design Flow - Part I

User Interface basics • Design entry methods • Schematics • The MegaWizard • Memory Editor • Project creation • Organisation and management • Basic settings • Editing HDL • Logic synthesis • Place and route (fitting)

Quartus II - Part II

Creating assignments & constraints • Dynamic checking • The Pin Planner o CSV import/export • Virtual pins • Creating and comparing revisions • Running Place and Route • Third party tool integration • Downloading and programming the target device • JTAG chains • Using non-Altera devices • Converting programming files and indirect JTAG programming (JIC)

Advanced use of Quartus II

Version-compatible databases • Optimisation options • WYSIWYG re-synthesis • Physical synthesis • Design analysis • Using the RTL, technology and state machine viewers • Cross-probing • Intelligent message suppression • Design rule checker (design rule assistant)

Design Flow Automation

For improved productivity and quality, design tasks and project management can be automated and secured with command-line scripts and Tcl scripts: Project creation • File management, archiving, cleanup, compilation, result testing, etc.

Simulation

Functional simulation and post-layout timing simulation with ModelSim • Quick overview of ModelSim AE (Altera Edition) • RTL simulation, compilation & simulation scripts • Adapting the test bench to the timing model • Generation & compilation of the VITAL model & SDF file

Day 2

Understanding and Mastering Quartus II's Timing Analysis

Timing analysis basics • Creating and managing constraints • The four types of analysis • Single and multiple clock domains • PLLs o Multi-cycle paths • Understanding the reports • Timing optimisation and getting rid of timing violations

Timing Analysis - Part II

Advanced concepts • Recovery/removal analysis • Timing exceptions • Latency vs offset analysis • Fast corner analysis • Slack calculation • Timing driven compilation • Multiple clocks • Harmonics & derived clocks • Clock uncertainty • Multicycle path with hold • Early timing estimation

Design Space Explorer

Concepts & use

Power Analysis and Optimisation

Using Powerplay • Early estimation & finer vector-based statistical estimation • Using the power optimisation adviser

In-System Memory Contents Editor

Concept • applications • how-to

SignalTap II

Take advantage of free Embedded Logic Analysers to debug your design. The three modes • Configuration • Using the Logic Analysis Interface • Capturing/displaying • Saving data • Taking advantage of the segmented mode • Using the MegaWizard

SignalTap - Part II

Advanced Triggering

SignalProbe

Signal Probe and the logic analyser interface • Purpose and use

Day 3

TimeQuest and SDC constraints

The new Static Timing Analyser • New concepts • New interface • Presentation of the Synopsys Design Constraints (SDC) format • SDC terminology • Using TimeQuest from the GUI and from SDC files • Understanding the TimeQuest reports • Practical applications to usual applications (constraining a single clock, input and output maximum and minimum delays, I/Os analysis, PLLs, etc..) · Early timing estimation

Incremental Compilation

Preparing a project for incremental flow • Creating design partitions • combining with floorplan constraints using LogicLock • exporting and importing a design • performance preservation • top-down and bottom-up flows

Optional: Techniques for Optimising Area and Timing

Making your RTL code more efficient • Optimising arithmetic • Resource sharing • Identifying and understanding the critical paths • Using the optimisation adviser • physical synthesis and advanced options • Tips for improving RTL coding

Course Dates:
April 28th, 2008	Munich, DE	Enquire
June 18th, 2008	Eindhoven, NL	Enquire
June 23rd, 2008	Bournemouth, UK	Enquire
July 14th, 2008	Munich, DE	Enquire
August 11th, 2008	Bournemouth, UK	Enquire