ARM Cortex-R4 SoC Design
Standard Level - 4 days
view dates and locationsARM Cortex-R4 SoC Design is a 4-day class for hardware engineers designing systems based around the ARM Cortex-R4 processor core. It includes an introduction to the ARM product range and supporting IP, programmer's model, instruction set architecture, AMBA on-chip bus architecture and the Cortex-R4 debug architecture. The class includes a number of worked examples to reinforce the lecture material.
Who should attend?
Hardware design engineers who need to understand the issues involved when designing SoC's around the ARM Cortex-R4 processor core.
Pre-requisites
Some knowledge of embedded systems and familiarity with digital logic and hardware/ASIC design issues. A basic awareness of ARM is useful but not essential.
Training materials
This class uses training materials developed by ARM®.
Content
- The ARM Architecture
- ARM CPU Architectures
- Memory Subsystems and Memory Management
- Cortex-R4 Overview
- Cortex-R4 Instruction Sets
- Exception Handling
- AXI Bus Architecture
- Primecell Vectored Interrupt Controller
- Processor Core
- L1 Subsystems
- L2 Interfaces
- Implementation
- Clocks, Reset and Power Management
- ARM v6 Memory Types
- Memory Protection
- Initialization
- Interrupts
- Multiprocessor Synchronization li type="disc">L2 Cache Controller
- CoreSight Debug Architecture Overview
- Debug and Trace
- ARM Processor Simulation Models
- Integration
This course is available now for team-based training at or near to your location. To find out more:
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