ARM Cortex-M3/M4 SoC Design
Standard Level - 3 daysview dates and locations
ARM Cortex-M3/M4 SoC Design is a 3-day class for engineers designing hardware based around the ARM Cortex-M3/M4 core. It includes an introduction to the ARM product range and supporting IP, programmer's model, instruction set architecture, AMBA on-chip bus architecture and Cortex-M3/M4 debug architecture. The class includes a number of worked examples developed by ARM® to reinforce the lecture material.
Who should attend?
Hardware design engineers who need to understand the issues involved when designing SoC's around the ARM Cortex-M3/M4 core.
Some knowledge of embedded systems and familiarity with digital logic and hardware/ASIC design issues. A basic awareness of ARM is useful but not essential.
This class uses training materials developed by ARM®.
Cortex-M3/M4 OverviewAn overview of the Cortex-M3 and Cortex-M4 processor cores that discusses the pipeline, memory map and other key features.
Cortex-M3/M4 CoreDetailing the processor pipeline and instruction execution.
ARMv7-M Exception HandlingIntroduces the exception handling model for Architecture v7-M. Explains how to write software handlers and manage interrupts.
Assembler ProgrammingOutlines the main features of the Thumb instruction set. Provides a primer for those needing to interpret compiler output or write low level code.
Cortex-M4 DetailsShowing the differences between Cortex-M3 and Cortex-M4. Introducing DSP and SIMD instructions, Floating Point Unit and extended exception stack frame.
AMBA AHB-LiteExplains the AMBA 3 AHB-Lite Bus protocol.
AMBA APBExplains the AMBA APB Bus protocol.
Cortex-M3/M4 System InterfacesDetailed discussion of the memory system bus interfaces at the processor and integration levels .
Cortex-M3/M4 Clocks, Reset PowerExplains the reset and clocking requirements and operation of sleep modes. Introduces the Wake-up Interrupt Controller.
Cortex-M3/M4 Memory ProtectionIntroduces the Memory Protection Unit. Explains memory types and attributes, and how to configure memory protection regions.
SysTick TimerIntroduces the built-in System Timer function and explains the calibration function.
Cortex-M3/M4 Debug and TraceIntroduces CoreSight and the DAP components and ROM Table. Overview of Debug and Trace capabilities and standard debug connectors.
Cortex-M3/M4 DebugDetailed view of debug capabilities, DAP components, and Flash Patch & Breakpoint Unit.
Cortex-M3/M4 TraceExplanation of instruction trace methodology. Detailed view of instrumentation trace and data watchpoint and trace units and trace port. Discussion of trace clocking.
Cortex-M3/M4 ExamplesBrief overview of Cortex-M3 example system and Cortex-M4 Integration Kit. Introduction to ‘tarmac’ and to multi-processor integration.
Cortex-M3/M4 ImplementationDetails of RTL configuration. Overview of design flow steps and introduction to Reference Methodologies.
Cortex-M system Design KitOverview of CMSDK components and example systems.
This course is available now for team-based training at or near to your location. To find out more:
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