Comprehensive SystemVerilog

Standard Level - 5 days

Auf Deutsch

SystemVerilog (IEEE 1800™) is a significant new language based on the widely used and industry-standard Verilog® hardware description language. The SystemVerilog extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in system design and architecture.

Comprehensive SystemVerilog provides a complete and integrated training program to fulfil the requirements of verification engineers and those wishing to evaluate SystemVerilog's applicability to both design and verification applications. It is structured to enable engineers to develop their skills to cover the full breadth of SystemVerilog features for both design and verification. This includes the requirements of verification engineers who wish to exploit the potential of class-based verification and object oriented techniques using SystemVerilog, as well as RTL coding, assertions and test benches. Design engineers who do not intend to use SystemVerilog for class-based verification should attend the shorter training course SystemVerilog for Design Groups, which shares the same content as Days 1 to 3 of Comprehensive SystemVerilog.

Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.

Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported for this course include:

Simulation: Cadence Incisive®, Mentor Graphics Questa™Sim, Synopsys VCS®
Synthesis: Mentor Graphics Precision™, Synopsys Design Compiler®, Synplicity Synplify®

Other tools may be available on request. Please contact Doulos if your preferred tools are not listed here.

Who should attend?

Design engineers who wish to make full use of SystemVerilog's class-based verification capabilities for test bench development as well as learning SystemVerilog for RTL design.
Verification engineers aiming to deploy coverage driven verification approaches for the first time using SystemVerilog
Verification engineers wishing to migrate to SystemVerilog class-based verification from other established verification languages and test bench automation techniques
Engineers and managers who wish to evaluate the full range of SystemVerilog's capabilities for design and verification
EDA support engineers who wish to gain a comprehensive understanding of how their customers' engineering teams can most productively use SystemVerilog in both design and verification domains

What will you learn?

The course is structured into several distinct sections.

Fundamentals of SystemVerilog for Design trains engineers in the practical use of SystemVerilog for synthesisable RTL design, and lays the foundations for use of the language in verification.
SystemVerilog Assertions teaches the principles of assertion-based verification and design, key features of the SystemVerilog assertion language for creating your own custom assertions, and how to package and deploy libraries of assertion checkers.
Module-based SystemVerilog Verification shows how to use SystemVerilog to build effective block-level testbenches, building on best-practice testbench architecture based on Verilog modules.
Class-based SystemVerilog Verification describes how to write sophisticated object-oriented testbenches using SystemVerilog's testbench automation capabilities, which support a constrained-random, coverage-driven verification methodology. These features enable you to write testbenches at higher levels of abstraction and be more productive than is possible with standard hardware description languages.

This course includes objective and up-to-date commentary on the three best-known published verification methodology approaches, and teaches key SystemVerilog language features that support them. In-depth training in specific methodologies can be provided by Doulos in partnership with leading vendors for onsite team-based requirements (see team-based training requirements outlined in the Doulos Modular SystemVerilog program). Contact Doulos to discuss your specific requirements.

Pre-requisites

A good working knowledge of Verilog is essential.

For engineers with no HDL knowledge or experience the Doulos Comprehensive Verilog course or equivalent is an essential precursor.

For engineers with no Verilog knowledge but with working experience of VHDL, Doulos offer a Fast Track Verilog for VHDL Users class in a format tailored to equip delegates with the necessary foundation for SystemVerilog. This class is usually scheduled in the same location prior to the Comprehensive SystemVerilog course. See Course Schedule for the latest scheduling information.

For onsite courses, precursor training in Verilog can be tailored to the specific team profile and combined with appropriate SystemVerilog modules to fully address team needs (see Modular SystemVerilog). Contact Doulos to discuss options that suit your needs.

Course materials

Doulos course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:

Fully indexed course notes creating a complete reference manual
Workbook full of practical examples and solutions to help you apply your knowledge
Doulos SystemVerilog Golden Reference Guide for language, syntax, semantics and tips

Structure and Content

Fundamentals of SystemVerilog for Design (Day 1 and day 2 morning)

The SystemVerilog data type system

enum • typedef • struct • union • packed/unpacked • packages and $unit • using arrays in SystemVerilog • array and structure literals, assignment patterns

Nets and variables

Key changes in Verilog-2005 and SystemVerilog • continuous assignment to variables • modified driver and connection rules • data types on ports and nets

Modules and processes

Port connection shorthand • type parameters • synthesis idioms for processes • miscellaneous improvements to the language

Design applications of interfaces

The interface construct • interfaces to encapsulate communication • modports • synthesis of interfaces and modports • imported functions for design

SystemVerilog Assertions (Day 2 afternoon)

Introduction to assertions

Assertions, properties, sequences • clocking and sampling • property implication • uses of assertions • simulation of assertions • formal tools

Assertion methodology

Methodology consequences of assertion-based design and verification • assertion and assumption • benefits of assertions to the designer • protocol checkers

A brief introduction to SVA syntax

Writing simple assertions of your own • sequences and the ## operator • repetition and time ranges • sequence fusion • overview of temporal operators • local variables and actions in assertions

Packaging Assertions

Assertions in interfaces and modules • the bind construct • deploying verification IP, particularly assertion-based IP

Module-based SystemVerilog Verification (Day 3)

Verification for design groups

Bus functional models • testbench architecture in classic Verilog • stimulus and response timing

Using SystemVerilog to construct module-level testbenches

Clocking and program blocks • testbench applications of interfaces • building libraries of stimulus patterns (sequences) • writing test cases to control the testbench

Dynamic data types

strings • queues • dynamic arrays • associative arrays • queue and array methods • foreach loop

Testbench automation

Brief introduction to testbench automation concepts • randomisation, checking and coverage • the need for constraints • randomisation of stimulus data using std::randomize and traditional Verilog distribution functions

Class-based SystemVerilog Verification (Days 4 and 5)

Introducing classes

SystemVerilog's class syntax • describing stimulus data and a stimulus generator • randomization of class members (without constraints) • objects and references • constructors and new • shallow copy using new • writing a custom copy method

Hooking classes to the DUT

Dynamically-constructed test environment vs. statically-elaborated DUT and test harness • using virtual interface and class-based BFMs • the role of clocking and program blocks • appropriate structure for DUT, clock generators and other structural elements • constructing and launching the test environment using program+initial • simple class-based testbench architecture

Advanced object-oriented features

Using inheritance to extend data classes • type parameterisation of classes • using virtual methods and polymorphism to create generic testbench infrastructure such as channels, FIFOs, scoreboards • deriving custom classes from generic base classes in a library such as AVM or VMM

Constrained randomisation

Full details of the SystemVerilog randomisation machinery, including inline and declarative constraints • dynamic control of constraints • using constraints as checkers • procedural randomisation: randcase, randsequence • control fields in classes for flexible constraints • constraints and inheritance

Modelling techniques

Process control in SystemVerilog: new forms of fork..join • spawning long-running threads with fork..join_none • other modelling support: built-in classes for linked-list, semaphore, mailbox • writing checkers and behavioural reference models

Class-based testbench architecture

Layered architectures - moving verification to higher levels of abstraction • relation between layering and self-contained verification IP • approaches taken by vendor-advocated methodologies (AVM, DTV, VMM) • moving transactions around a testbench • unifying ideas: transaction ports, transaction FIFO, design pattern for publisher/subscriber, callbacks for snooping and error injection • base classes for transaction, transactor, environment • automating the activity of testbench components

Coverage and planning

Coverage-driven TBA methodology • coverage planning as the first step in a verification process • SystemVerilog coverage constructs in detail • analysing and interpreting coverage data

Course Dates:
April 21st, 2008	Munich, DE	Enquire
May 19th, 2008	Austin, TX	Enquire
June 9th, 2008	Munich, DE	Enquire
June 23rd, 2008	Bournemouth, UK	Enquire
June 23rd, 2008	Nice, FR	Enquire
July 7th, 2008	Eindhoven, NL	Enquire
July 14th, 2008	San Jose, CA	Enquire
August 4th, 2008	Munich, DE	Enquire