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Expert SystemC Modelling

Advanced Level - 2 days

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 Auf Deutsch

Expert SystemC Modelling is a 2-day advanced training course focussing on the application of SystemC to Transaction Level Modelling (TLM). The major benefits of SystemC include architectural exploration and performance modelling of complex Systems-on-Chip, and the ability to run software at speed on a virtual model of the hardware platform prior to the availability of RTL code. These benefits are enabled by the use of Transaction Level Modelling. In this course, you will learn the techniques required to build SystemC TLM models of bus-based SoC platforms at key abstraction levels.

This course builds on and complements the knowledge taught in the Doulos Comprehensive SystemC course. It is appropriate to attend Expert SystemC Modelling within a few weeks or months of attending Comprehensive SystemC.

Expert SystemC Modelling is based on version 2.1v1 of the OSCI TLM Standard and SystemC class library. The course introduces features from the IEEE Std 1666 and SystemC version 2.2. The course explores the latest thinking in the standardisation of TLM interfaces and modelling styles.

Course workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. Delegates can use the tools and platform of their choice on all exercises and workshops.

Engineers interested in verification using SystemC should attend the Doulos Expert SystemC Verification course, which covers the SystemC Verification class library (SCV).

Doulos has a world-wide lead in independent SystemC know-how having been active in SystemC-based methods since 2000. We have delivered SystemC training and support to engineers in more than 100 companies world-wide - including direct involvement with methodology and tool developers in such companies as ARM, Cadence, CoWare, Mentor Graphics and Synopsys

Who should attend?

  • Hardware, software and systems engineers who are familiar with the SystemC class library and want to learn to use SystemC more effectively for Transaction-Level Modelling.

What will you learn?

  • How to choose the appropriate abstraction levels for your particular modelling tasks
  • How to exploit the emerging standards for Transaction-Level Modelling
  • How to write Transaction-Level Models of common System-on-Chip platform components such as busses, masters and slaves
  • The features of SystemC versions 2.1, 2.2 and the OSCI TLM interface standard for Transaction-Level Modelling
  • How to optimise a SystemC model for compilation and simulation speed

Pre-requisites

Delegates need a good working knowledge of C++ and of the SystemC class library. Prior attendance of Doulos Comprehensive SystemC training course (or equivalent) is required.

Please contact Doulos direct to discuss and assess your specific experience against the Pre-requisites.

Course materials

Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Fees include
  • Fully indexed course notes creating a complete reference manual
  • Workbook full of practical examples and solutions to help you apply your knowledge
  • Doulos SystemC Golden Reference Guide for language, syntax, semantics and tips.

Structure and Content

Day 1

Introduction - Transaction-Level Modelling

Definition of TLM • TLM abstraction levels and use cases • The Functional, Architectural, Programmers and Verification Views • Principles of TLM • Implementing transactions using unidirectional transfers and copy semantics • Blocking and non-blocking function calls • Transport layer modelling and the OSCI TLM standard

SystemC Reprise

A reprise of SystemC features useful for TLM • Hierarchical, primitive and minimal channels • Using ports and exports • Features of the sc_interface class • Implementing design rule checks • Creating specialised ports • Creating and using event finders • User-defined primitive channels • Spawning dynamic processes • Process termination

The Programmers View

The assumptions behind the PV use case • Creating a deterministic system model • Synchronisation between multiple masters • PV versus PVT • The bidirectional blocking transport interface • Passing request and response objects • Implementing PV masters and slaves • Implementing the PV convenience layer of initiator ports and slave base classes • Implementing a PV router • The TAC protocol

The Architectural View

AV characteristics • Modelling architectures with two-ended TL- channels • Active versus passive models • The unidirectional blocking and non-blocking interfaces • The OSCI TLM request-response channel and FIFO channel • The OSCI TLM interface inheritance hierarchy • Using master and slave exports

Day 2

AV Timing

The OCP TLM APIs • Annotating timing onto the protocol layer • Modelling latency and recovery times • Explicit versus implicit timing models • PV-AV adapters and the OSCI transport channel

Arbitration and Routing

Blocking versus non-blocking arbiter implementations • The generic OSCI TLM arbiter • Creating sensitivity to multiple channels • Implementing TLM routers • Transport layer plug-and-play

The Cycle Accurate Level

CA characteristics • Two-phase simulation semantics and the request-update mechanism • Using sc_signals • CA coding tricks and traps • PV-CA adapters

Creating SystemC IP

Optimising compilation speed • Optimising simulation speed • Selecting data types and channels • Hiding implementation details in deployed IP • Forward declarations • Optional ports • Parameterised modules • Issues with class templates • Using the non-templated base classes

Course Dates:
May 15th, 2008   San Jose, CA    Enquire
June 16th, 2008   Paris, FR    Enquire
July 28th, 2008   Bournemouth, UK    Enquire
July 28th, 2008   Munich, DE    Enquire
August 11th, 2008   San Jose, CA    Enquire

Price on request


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