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Expert Verilog

Advanced Level - 4 days

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 Auf Deutsch

Expert Verilog is an intensive 4-day advanced application course. It teaches engineers how to increase productivity by enhancing their Verilog coding and application skills. Presented in two distinct modules, Expert Verilog focuses on language and synthesis issues, design re-use, test benches and the latest verification techniques including PSL and an introduction to modern assertion-based approaches to verification. Each module also includes an overview of the 2001, 2005 and SystemVerilog extensions to Verilog, with an assessment of their impact on both design and verification.

  • Expert Verilog Design (2 days) for design engineers wishing to deepen their knowledge of both RTL and synthesis using Verilog, and to improve their Verilog coding style with design re-use in mind. Design for Verification is also covered with an Introduction to PSL and modern assertion-based techniques.

  • Expert Verilog Verification (2 days) for design engineers and verification engineers involved in Verilog test bench development, or behavioural modelling, for the purpose of functional verification.

The modules, which may be attended together or independently, follow on from the industry standard Doulos course, Comprehensive Verilog. Carefully designed workshops comprise 50% of teaching time, and enable engineers to apply their new skills in the context of the latest Verilog design tools, practices and methodologies.

Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:

  • Aldec Active HDL™ & Riviera-PRO™
  • Cadence Incisive®
  • Mentor Graphics ModelSim® & Questa®
  • Synopsys VCS®
  • Synopsys Synplify Pro®
  • Synopsys Design Compiler®
  • Mentor Graphics Precision® RTL

The tool options available on a specific scheduled course may vary. Preferences can be selected in the booking process. Or please contact Doulos to discuss specific requirements.

Who should attend?

  • Design engineers wishing to improve the efficiency of their hardware designs and increase productivity
  • Design and verification engineers who want to structure and write effective test environments to verify complex designs and systems

What will you learn?

  • A deeper understanding of the Verilog language and how to apply it, enabling you to troubleshoot Verilog simulation and synthesis problems more easily.
  • How to produce smaller and faster hardware designs using Verilog with RTL synthesis tools.
  • A Verilog coding style to facilitate code re-use and best practice in how to package IP.
  • How recent revisions of the Verilog language and the SystemVerilog extensions will impact and enhance your design and verification activity
  • How best to tackle the problem of design verification using Verilog - the principles and practice.
  • Techniques for writing behavioural models of hardware components in Verilog.
  • How to incorporate PLI applications into your Verilog simulations.


This is an advanced language and methodology training course. Prior attendance of the Doulos Comprehensive Verilog course (or equivalent) is required, and at least 6 months of 'live' project experience using Verilog is strongly recommended. Delegates attending the Expert Design module must have knowledge and experience of register transfer level coding and synthesis, using Verilog.

Course materials

Doulos Course materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course materials include:
  • Fully indexed course notes creating a complete reference manual
  • Workbook full of practical examples to help you apply your knowledge
  • Doulos Golden Reference Guide for language syntax, semantics and tips
  • Complimentary PSL Golden Reference Guide, which include coverage of OVL
  • Tool & technology tour booklets (to support the tools and technologies of your choice)

Structure and Content

Expert Verilog Design (days 1-2)

RTL Design with Verilog

The RTL subset - writing synthesis-friendly code • Incomplete assignment, latches and re-circulation • Asynchronous inputs to clocked processes • Inference versus instantiation • The limits of combinational, register and arithmetic optimisation • Timing constraints, area constraints, and optimisation options • Multiple clocks and partitioning clock domains • Synthesis methodology for large designs

RTL Coding Styles

Coding styles for efficient and maintainable designs • Using local variables • Blocking and non-blocking assignments - recommendations, pitfalls and myths

State Machine Design

Implementing sequential algorithms in RTL • Coding styles and design tradeoffs for Finite State Machines

IP and Re-use with Verilog

Language level re-use • Standard component re-use • Impact of IP on design process • Writing re-usable Verilog • RTL Verilog style for capturing IP • Isolating tool and technology dependencies • Readability and maintainability • Comments and meaningful names • Language facilities for re-use, including Verilog-2001 improvements

Design for Verification with Assertions

Why use assertions in your designs? • Introduction to Properties • Property Specification Language (PSL) and SystemVerilog Assertions (SVA) • Introduction to temporal operators • Embedding assertions in your designs

Verilog-2001, Verilog-2005 and SystemVerilog for Design

A tutorial review of recent changes in the Verilog language that are relevant to design • Preview of SystemVerilog design enhancements

Expert Verilog Verification (days 3-4)

Verification Strategies

Verification flow • Black and white box testing styles • Code analysis to guide testing • Techniques for stimulus generation and output checking

Advanced Verilog for Verification

Fine-grain concurrency with fork/join • The Verilog simulation cycle and its impact on coding style • Non-determinism and race hazards • Understanding the effect of delayed signal assignments

Improving the Quality of your Test Fixture Code

Structuring test fixtures with tasks and functions • Tactics for packaging code for maintainability and re-use • Advanced stimulus generators: serial data, complex timing • Software encapsulation: modules, local variables, multiple hierarchies

Transaction-Based Test Fixtures

Bus functional models • Techniques for layering your test fixtures • Using Verilog modules like OO classes • Transaction generation using bus functional models • Re-use and flexibility of test fixture code


Specify blocks • Built-in timing checks • Strobing inputs and sampling outputs • Measuring delays • Storing inputs/outputs in a buffer • Collecting and filtering diagnostic data • Simple data visualisation techniques

Component Modelling Introduction

Uses of component modelling • Component modelling methods • Choosing a component model • Structure of a component model • Handling asynchronous inputs • Storing inputs/outputs and sampling outputs • Measuring delays

Modelling and Analysis Techniques

Modelling memories • Imitating dynamic allocation in Verilog • Using public domain PLI applications to model large memories • Modelling external analogue subsystems • Signature analysis and other techniques for regression testing • Varying the timing of stimulus • Modelling communcations channels • Random and directed-random tests

Using PLI Libraries

(note: no prior experience of C is assumed)
Incorporating PLI applications into your simulations • What the PLI can and can’t do • Two generations of the PLI – which to use? • Types of PLI application: functions, stimulus generators, file access, component models • Pointers to functions in C • Function pointer tables • PLI application integration in various simulators

Verilog-2001, Verilog-2005 and SystemVerilog for Verification

A tutorial review of recent changes in the Verilog language that are relevant to verification • Preview of SystemVerilog verification extensions

Optional modules - (Expert Verification)

To meet varying specialist interests for team-based training, one or more of these optional modules can be integrated with the course by prior agreement with Doulos. These options are not available on scheduled public courses.

Modelling Analogue Hardware

Verilog drive strengths • Modelling I/O primitives such as open-drain and pullup • Verilog switch primitives • Simulating the external analogue world using real numbers and sampled-time

Verilog File I/O

Review of Verilog-1995 file I/O mechanisms • Verilog-2001 file I/O model and file reading functions • Reading structured data from text files • File-driven test fixtures

Writing PLI Applications

The PLI option requires a working knowledge of the C programming language.
PLI jargon • VPI and TF/ACC routines • Creating a simple PLI application • Linking PLI code to your Verilog simulation • Callback functions • Stimulus generators • Making PLI applications sensitive to input changes • Writing component models in the PLI

Looking for team-based training, or other locations?

Complete an on-line form and a Doulos representative will get back to you »

Price on request

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