Expert VHDL Verification

Advanced Level - 3 days

Auf Deutsch

Expert VHDL Verification is an intensive advanced application course. It teaches engineers how to increase productivity by enhancing their VHDL coding and application skills. The syllabus focuses on test benches and ‘hot’ techniques for verification such as scoreboarding and Transaction Level Verification (TLV).

Carefully designed workshops comprise 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.

Expert VHDL Verification forms the last 3 days of the 5-day Doulos Expert VHDL course.

Who should attend?

Design engineers and verification engineers involved in VHDL test bench development or behavioural modelling for the purpose of functional verification

What will you learn?

A set of VHDL language features that go beyond what is taught on a basic training class
The principles and details of how to approach the problem of design verification using VHDL
How to structure and write large and complex VHDL test benches
The principles and details of how to write behavioural models of hardware components in VHDL
A deeper understanding of the VHDL language and how to apply it, enabling you to troubleshoot VHDL simulation problems with ease

Pre-requisites

To maximise the training value, prior attendance of the Doulos Comprehensive VHDL (or equivalent) course is required.

Course materials

Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:

Fully indexed course notes creating a complete reference manual
Workbook full of practical examples to help you apply your knowledge
Doulos VHDL Golden Reference Guide for language, syntax, semantics and tips
Tour guides (to support the tools and technologies of your choice)

Structure and Content

VHDL Language

Subprograms, parameters, assigning signals • User defined packages • User defined array types • Record types, selected names, aggregates, arrays of records • Types, subtypes and overloading, conversion functions • Qualified expressions • Generics, string generics, array generics Configurations, binding and dependencies, generic and port maps

Test Benches

The Verification Plan • Structure of a simple test bench • Structure of a complex test bench • Procedural stimulus generation • Reactive test benches • File I/O; TEXTIO and ‘C’ • Measuring delays • Monitoring internal signals • Generating random numbers • Collecting diagnostic data • Storing inputs/outputs in a buffer • Tagging data and Scoreboards • Coping with latency and Out-of-Order completion • Control files • Adding a user interface to a test bench • Instantiating behavioural models • Generic and parameterised test benches

How VHDL works

Signal assignments • Events and inertial delay • Deltas Drivers and resolution functions • Wait statements • NOW • Static elaboration, the network model • Dynamic elaboration, elaborating arrays and files in subprograms

Component Modelling

How to structure a behavioural model • Structuring a process to respond to external events • Handling asynchronous or unpredictable inputs • Representing state • Representing fixed and floating point numbers, instruction words, bit-serial data, frames, analog signals • Giving visibility of internal state • Simulation speed • Modelling external timing relationships • Checking timing constraints using signal attributes • 1164 strength strippers • Handling ‘X’ on the inputs • Modelling memories • Modelling analogue blocks • Modelling interfaces for inclusion in a test bench Bus-functional models • Processor models • Foreign bodies for including C models for interfacing to emulators • Hardware/software co-simulation

Course Dates:
May 7th, 2008	Munich, DE	Enquire
May 28th, 2008	Grenoble, FR	Enquire
June 18th, 2008	Cambridge, UK	Enquire
August 6th, 2008	Bournemouth, UK	Enquire