Download as PDF

Modular SystemC

Inhouse Trainingsoptionen

Advanced Level

view dates and locations
 Auf Deutsch

Modular SystemC is a set of training modules related to SystemCTM aimed at fulfilling team-based training requirements for engineers from a range of technical backgrounds, i.e hardware and software engineers and system architects. It consists of two primer modules and three SystemC modules from which a single program can be created to fit the specific training requirements of the team.

Modular SystemC is a hands-on training class that is presented from a vendor independent perspective but with practical workshops that support a choice of the leading EDA tools.The Modular SystemC package is only available for in-house or customer-dedicated training. The modules comprise.

  • Essential C++ for SystemC (2 days) takes engineers who have a basic knowledge of the C programming language and gives them a fast-track way to acquire a good grounding in C++, which is an essential foundation for learning SystemC.

  • Fundamentals of SystemC (3 days) builds on the foundation laid by Essential C++ to prepare the engineer for the practical use of SystemC for transaction-level modelling. This module describes the core SystemC v2.1 class library and its application for modelling systems, communication, hardware and software at the transaction-level, and refinement towards hardware-software implementation.

  • Expert SystemC Modelling (2 days) builds on the foundation laid by the Fundamentals of SystemC. Covering the new Transaction Level Modelling (TLM) standard in detail, it shows how to use SystemC more effectively, focusing on how to code for compilation, simulation speed and IP re-use.

  • Expert SystemC Verification (2 days) Expert SystemC teaches the use of SystemC for testbench automation using a constrained random verification methodology. This course, based on versions 2.0.1 and 2.1 of the SystemC class library and version 1.0p001 of SCV and version 5.3s001 of CVE, teaches delegates how to debug and validate models, and exploit the SystemC Verification Library (SCV).

Based on these modules, team-based and in-house training can be customised to fit the content, scope and duration needed to best-fit a specific customer requirement. In particular, the following SystemC topics can be emphasised if desired:
  • Hardware synthesis from SystemC, including both RTL and behavioural synthesis
  • An in-depth focus on the mechanisms used in the SystemC class libraries. This is aimed at specialists who wish to develop their own channel models and at those intergrating the SystemC classes into other simulation environments.
  • Using the SystemC Verification library (SCV)
  • Building a transaction level model of a tupical bus-based platform with multiple masters at various levels of abstraction (PV, PVT, CA etc)

Workshops within the course are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. The workshops can be provided in the context of the customer’s own choice of tools and supplemental tool training can be arranged in collaboration with the vendor if needed.

Please contact Doulos to discuss specific tool requirements.

Who should attend?

  • Hardware design engineers who wish to become skilled in the practical use of SystemC for digital hardware design and verification.
  • System engineers and architects who wish to become skilled in the practical use of SystemC for system level modelling.
  • Software engineers who already have good knowledge of C/C++, but wish to acquire some practical experience in the use of the SystemC class libraries.
  • Hardware, software and systems engineers who are familiar with the SystemC class library and want to learn to use SystemC more effectively for Transaction-Level Modelling.

What will you learn?

  • The C++ language features necessary to master SystemC
  • Object-oriented programming techniques as used by the SystemC class libraries
  • The SystemC core language, data types and channels
  • How to make best use of the SystemC simulator and SCV to debug and validate your models
  • The features of SystemC version 2.1 and the OSCI TLM interface standard for Transaction-Level Modelling
  • How to write Transaction-Level Models of common System-on-Chip platform components such as busses, masters and slaves.
  • How to choose the appropriate level of abstraction for a Transaction-Level Model
  • How to refine SystemC models between multiple levels of abstraction
  • Gain an introduction to hardware synthesis using SystemC
  • How to code for compilation, simulation speed and IP re-use
  • The SCV core classes and facilities
  • The additional features in Cadence Verification Extensions (CVE 5.3s001)

Pre-requisites

  • Essential C++ for SystemC Delegates need basic knowledge of the C programming language; in particular, familiarity with C functions, variables, data types, operators, and statements. Recent hands-on experience of another similar programming language such as Java, or beharioural-style HDLs is advantageous. This module is suitabel for people with no previous knowledge of C++ or as a refresher for those with limited knowledge of C.

  • Fundamentals of SystemC A working knowledge of C++ and of object-oriented programming concepts is essential and basic knowledge of hardware design is recommended. Prior attendance of the Doulos ‘Essential C++’ course (or equivalent) is required. Delegates with C++ experience should check their knowledge against the ‘SystemC C++ Pre-requisites’, available from Doulos, before attending. The course is suitable for electronic hardware, software or systems engineers, but in order to gain maximum benefit from this course, delegates should be active users of either a high-level software programming language (ideally C++) or a hardware description language (VHDL or VerilogŪ)

  • Expert SystemC Modelling Delegates need a good working knowledge of C++ and of the SystemC class library. Prior attendance of Doulos Comprehensive SystemC training course (or equivalent) is required.

  • Expert SystemC Verification Delegates must have a good working knowledge of C++ and SystemC. Prior attendance of the Doulos Comprehensive SystemC training course (or equivalent) is required. No previous knowledge of constrained random verification is needed, as this will be introduced during the course.

Course materials

Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. Fees include:
  • Fully indexed course notes creating a complete reference manual
  • Workbook full of practical examples and solutions to help you apply your knowledge
  • Doulos SystemC Golden Reference Guide for language, syntax, semantics and tips.

Structure and Content

Essential C++ for SystemC (2 days)

Day 1

Learn about the differences between C and C++

From C to C++

The features added to C by C++ and the ANSI C-1999 standard • const • bool • Header files • Namespaces • The global and standard namespaces • Stream I/O

Functional and Pointers

Learn how functions and dynamic memory allocation have changed in C++ • Pass-by-reference • Function prototypes • Default arguments • Function overloading • Operator overloading • Static, automatic and dynamic storage • new • delete

The C++ Standard Library

Learn to make the most of the built-in standard classes • Container classes • Examples of using the standard vector class • Examples of using the standard string and stringstream classes

Classes and Objects

Learn the principles of object-based design • Information hiding • Abstract data types • Classes and objects • Public and private class members • Member functions • Scope resolution

Day 2

Master the subtleties of object-oriented programming in C++

Class Members

Master the C++ mechanisms associated with classes • Constructors • Destructors • Copy constructors • Pointers versus objects • Friends • this • Overloading operators as members • Static members • Constant objects and members

Inheritance

Learn to exploit the power of object-oriented programming • Class relationships • Initializing sub-objects • The default constructor • Derived classes • Inheritance • Protected members • Up- and down-casting • Order of initialization

Virtual Functions

Delve deeper into object-oriented programming techniques • Overriding methods • Virtual functions • Polymorphism • Run-time type identification • Abstract base classes • Multiple inheritance

Further C++ Features

Advanced C++ features used in the SystemC class libraries • Function templates • Class templates • Implicit conversions • User-defined conversions • Exceptions

Fundamentals of SystemC (3 days)

Day 3

Become proficient in using the features of SystemC

Introduction to SystemC

Learn the background to SystemC and how SystemC fits into the system-level design flow • The architecture of the SystemC release • The benefits and risks of adopting SystemC • The objectives of transaction-level modelling

Getting Started

Learn how SystemC source code is structured and how to organise files • SystemC header files and namespaces • Compiling and executing a SystemC model

Modules and Hierarchy

How to describe the structural connections between modules • Modules • Ports • Processes • Signals • Methods • Primitive channels • Module instantiation • Port binding

Processes and Time

Describing concurrency and the passage of time • SC_METHOD • SC_THREAD • Event finders • Static and dynamic sensitivity • Time • Events • Clocks • Dynamic processes

The Scheduler

Gain an insight into how SystemC manages the scheduling of processes and events • Starting and stopping simulation • Elaboration and simulation callbacks • The phases of simulation • Event notification • Event queues • wait and next_trigger

Day 4

Learn to apply SystemC to modelling data, communication and busses.

Debugging and Tracing

Learn about the facilities provided by SystemC to ease debugging and diagnostics • Debugging techniques • The standard reporting mechanism • Error handling • Writing trace (vcd) files • Tracing buried signals and local variables • Using waveform display tools

SystemC Data Types

Data types for bit-accurate and hardware modelling • Signed and unsigned integers • Limited and finite precision integers • Assignment and truncation • Type conversion • Bit and part selects • Concatenation • Bit and logic vectors • Hexadecimal numbers • Avoiding common pitfalls • Bus resolution • Fixed point types

Interfaces and Channels

Learn how channels are used to abstract communication and create fast simulation models • Hierarchical, primitive and minimal channels • Interface method calls • SystemC interfaces • Port-less channel access • The SystemC object hierarchy • The class sc_port • Registering ports • How to make the most of ports, channels and interfaces

Day 5

Exploration of the application of Transaction-Level Modelling

Bus Modelling

Learn the techniques required to write and use bus models in SystemC • Master and slave interfaces • The execution context of interface method calls • Blocking and non-blocking methods • Using events and dynamic sensitivity within channels • Multi-ports • Port binding policies • sc_export

Refinement

An example of refinement from a C algorithm through untimed and timed SystemC models down to a mixed hardware-software implementation • SystemC wrappers • Timing annotation • Using sc_buffer • Structural refinement, communication refinement, and data refinement

Adapters

Channel refinement using adapters • Events versus event finders • Instantiating and binding adapters

Transaction-Level Modelling

The transaction-level modelling space • The functional, architecture, programmers and verification views • TLM principles • Transactions versus transfers • Passing request and response objects • The OSCI TLM standard • The standard blocking, non-blocking and transport interfaces • Implementing the transport and protocol layers

Supplementary Subjects

Fixed Point Types

Fixed point word length and integer word length • Quantization modes • Overflow modes • Fixed point context • The type cast switch • Utility methods

Overview of SystemC Synthesis

RTL versus behavioural synthesis technology • The work of the OSCI synthesis working group • Synthesizable data types • Clocked threads and resets • Restrictions

Overview of the SystemC Verification Library

Introduction to and aims of SCV • Constrained random verification methodology • Extended data types to support introspection • Randomization • Transaction Recording

Expert SystemC Modelling (2 days)

Day 1

Introduction - Transaction-Level Modelling

Definition of TLM • TLM abstraction levels and use cases • The Functional, Architectural, Programmers and Verification Views • Principles of TLM • Implementing transactions using unidirectional transfers and copy semantics • Blocking and non-blocking function calls • Transport layer modelling and the OSCI TLM standard

SystemC Reprise

A reprise of SystemC features useful for TLM • Hierarchical, primitive and minimal channels • Using ports and exports • Features of the sc_interface class • Implementing design rule checks • Creating specialised ports • Creating and using event finders • User-defined primitive channels • Spawning dynamic processes • Process termination

The Programmers View

The assumptions behind the PV use case • Creating a deterministic system model • Synchronisation between multiple masters • PV versus PVT • The bidirectional blocking transport interface • Passing request and response objects • Implementing PV masters and slaves • Implementing the PV convenience layer of initiator ports and slave base classes • Implementing a PV router • The TAC protocol

The Architectural View

AV characteristics • Modelling architectures with two-ended TL- channels • Active versus passive models • The unidirectional blocking and non-blocking interfaces • The OSCI TLM request-response channel and FIFO channel • The OSCI TLM interface inheritance hierarchy • Using master and slave exports

Day 2

AV Timing

The OCP TLM APIs • Annotating timing onto the protocol layer • Modelling latency and recovery times • Explicit versus implicit timing models • PV-AV adapters and the OSCI transport channel

Arbitration and Routing

Blocking versus non-blocking arbiter implementations • The generic OSCI TLM arbiter • Creating sensitivity to multiple channels • Implementing TLM routers • Transport layer plug-and-play

The Cycle Accurate Level

CA characteristics • Two-phase simulation semantics and the request-update mechanism • Using sc_signals • CA coding tricks and traps • PV-CA adapters

Creating SystemC IP

Optimising compilation speed • Optimising simulation speed • Selecting data types and channels • Hiding implementation details in deployed IP • Forward declarations • Optional ports • Parameterised modules • Issues with class templates • Using the non-templated base classes

Expert SystemC Verification (2 days)

Verification Methodology

Black and White Box Testing • Simulation and coverage • Verification Methodology Overview • What is Testbench Automation? • How SystemC and SCV fit in to verification • Obtaining SCV

Data Introspection

Extensions to data • Static vs Dynamic extensions • Extensions components • Extending built-in data types • Extending User Defined Data Types • User-defined data types with private attributes • Accessing Static Data Extensions

Randomization

Randomization • Dynamic extensions • Shared (reference-counted) pointers • Smart Pointers • Randomizing user defined data • Weighted distributions using bags • Weighted distributions using keep • Reproducibility • Using Seed Files

Constraints

Why we need constraints • Hard vs Soft • Creating constraints - scv_constraint_base • Constraining a simple data type • Constraining a user data type • Enabling and disabling constraints • Methods vs attributes • Overloading next() • Hierarchical Constraints

Transaction Recording

Requirements for transaction recording • Stream, generators, databases • Creating output • Transaction attributes • Using the transaction database

Other SCV Features

Using SCV_REPORT • The HDL Connection API • SCV data types (scv_sparse_array)

SystemC 2.1 Dynamic Threads

Dynamic Thread Applications • Spawning Threads and Methods • Setting spawn options • Spawning functions • Spawning member functions • scx_barrier

Cadence Verification Extensions (CVE) [optional]

CVE Wizards • Connecting to ncsim • Recording to an SDI database • Dynamic Thread Creation • Other data types (smart queues)

Doulos acknowledges trademarks and registered trademarks are the property of their respective owners


No public course dates are currently scheduled

Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

Price on request


Back to top