Modular SystemVerilog

In-house Training Module Options

 Auf Deutsch

SystemVerilog (IEEE 1800™) is a significant new language based on the widely used and industry-standard Verilog® hardware description language. The SystemVerilog extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in system design and architecture.

Modular SystemVerilog consists of several modules that can be combined and customised into an integrated program to fulfil team-based training requirements. Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.

Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported for this course include:

• Simulation: Cadence Incisive®, Mentor Graphics Questa™Sim, Synopsys VCS®
• Synthesis: Mentor Graphics Precision™, Synopsys Design Compiler®, Synplicity Synplify®

Other tools may be available on request. Please contact Doulos if your preferred tools are not listed here.

Who should attend?

• Engineers and managers who wish to evaluate the full range of SystemVerilog's capabilities for design and verification
• EDA support engineers who wish to gain a comprehensive understanding of how their customers' engineering teams can most productively use SystemVerilog in both design and verification domains

What course modules are available?

• Verilog for VHDL Users (1-3 days) provides a secure grounding in the essentials of the classic Verilog language, enabling engineers whose HDL experience has been predominantly in VHDL to gain maximum benefit from SystemVerilog training modules.
• Fundamentals of SystemVerilog for Design (1 ½ days) trains engineers in the practical use of SystemVerilog for synthesisable RTL design.
• Fundamentals of SystemVerilog for Verification (½ day) provides verification engineers with the necessary background in SystemVerilog to embark on the remaining verification modules.
• SystemVerilog Assertions (½ day) teaches the principles of assertion-based verification and design, key features of the SystemVerilog assertion language for creating your own custom assertions, and how to package and deploy libraries of assertion checkers.
• Module-based SystemVerilog Verification (1 day) shows how to use SystemVerilog to build effective block-level testbenches, building on best-practice testbench architecture based on Verilog modules.
• Class-based SystemVerilog Verification (2 days) describes how to write sophisticated object-oriented testbenches using SystemVerilog's testbench automation capabilities, which support a constrained-random, coverage-driven verification methodology. These features enable you to write testbenches at higher levels of abstraction and be more productive than is possible with standard hardware description languages.
• Adopter Classes (2-3 days) provide vital additional information, code examples and know-how to enable you to deploy popular vendor-advocated verification methodologies such as OVM (Mentor & Cadence), AVM (Mentor), URM (Cadence) and VMM (Synopsys).

This course includes objective and up-to-date commentary on the three best-known published verification methodology approaches, and teaches key SystemVerilog language features that support them. In-depth training in specific methodologies can be provided by Doulos in partnership with leading vendors for onsite team-based requirements (see team-based training requirements outlined in the Doulos Modular SystemVerilog program). Contact Doulos to discuss your specific requirements.

Pre-requisites

A good working knowledge of Verilog is essential. Engineers already proficient in VHDL can follow the 2-day module Fast-track Verilog for VHDL Users to meet this prerequisite. For engineers with other backgrounds Doulos can offer tailored Verilog training, either as a separate course or integrated into a team-based training package. Contact Doulos to discuss the options that best suit your needs.

Which modules should you choose?

The modular packaging allows Doulos to work flexibly with you to prepare a customised training course that matches your specific needs. We have carefully planned two standard tracks to meet the majority of training requirements and you are invited to consider one of these as a starting point for any discussion about customisation:

Design Group Track (3-5 days)

This track is designed to meet the needs of RTL design teams who wish to use SystemVerilog to enhance their designs, and who expect to create design-specific module-level testbenches using SystemVerilog to improve verification productivity and quality.

• Verilog for VHDL Users (if required)
• Fundamentals of SystemVerilog for Design
• SystemVerilog Assertions
• Module-based SystemVerilog Verification

Verification Specialist Track (4-7 days)

This track is focused on the needs of verification teams who wish to use SystemVerilog either to move their verification activity forward to use modern testbench automation techniques, or who aim to use SystemVerilog to replace other testbench solutions. It assumes delegates are already proficient in VHDL or Verilog - contact Doulos to discuss options for those who don't meet this prerequisite.

• Verilog for VHDL Users (if required)
• Fundamentals of SystemVerilog for Verification
• SystemVerilog Assertions
• Module-based SystemVerilog Verification
• Class-based SystemVerilog Verification
• Adopter Class (optional)

Course materials

Doulos course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:

• Fully indexed course notes creating a complete reference manual
• Workbook full of practical examples and solutions to help you apply your knowledge
• Doulos SystemVerilog Golden Reference Guide for language, syntax, semantics and tips

Structure and Content

Verilog for VHDL Users (1-3 days)

Introduction

What is Verilog? • brief history and current status • the PLI • scope of Verilog • design flow • Verilog-2001 • SystemVerilog • Verilog books and Internet resources

Differences between VHDL and Verilog

"Philosophy" • red tape • strong typing • determinism • data abstraction • dtructure vs behaviour - nets vs registers • language structure - architecture, packages, configurations, files • identifiers • output ports • implicit wires • arrays • aggregates • signedness • operators • signal vs variables/nets • process vs initial/always • if, case, loop differences • file i/o • hierarchical names

Verilog basics

Modules & ports • continuous assignments • comments • names • nets and strengths • design hierarchy • module instances • primitive instances • text fixtures • $monitor • initial blocks • logic values • vectors • registers • numbers • output formatting • timescales • always blocks • $stop and $finish • using nets and variables correctly

Combinational logic

Event control • if statements • begin-end • incomplete assignment and latches • unknown and don't care • conditional operator • tristates • case, casez and casex statements • full_case and parallel_case directives • for, repeat, while and forever loops • integers • self-disabling blocks • combinational logic synthesis

Sequential logic

Synthesising flip-flops & latches • avoiding simulation race hazards • nonblocking assignments • asynchronous & synchronous resets • clock enables • synthesizable always templates • designing state machines • state machine architectures • Verilog code-based FSM strategy • state encoding • unreachable states & safe design practices • one-hot machines

Other features of Verilog

Verilog operators • part selects • concatenation & replication • shift registers • conditional compilation • parameterisation and generate • hierarchical names • arithmetic operators and their synthesis • signed and unsigned values • memory arrays • RAM modelling and synthesis • $readmemb and $readmemh

Tasks and functions

Understanding tasks • task arguments • task synchronization • tasks and synthesis • functions

Test fixtures

File I/O - writing to files; file access using MCDs; reading from files • automated design verification using Verilog • force and release • gate-level simulation • back annotation using SDF • "traditional" Verilog libraries • configuration and libraries • command-line options • behavioural modelling

Behavioural Verilog

Algorithmic coding • synchronization using waits & event control • concurrent-disabling of always blocks • named events • fork & join • high-level modelling using tasks, implicit FSMs and concurrent-disabling • understanding intra-assignment controls • overcoming clock skew • blocking and nonblocking assignments • continuous procedural assignment

Fundamentals of SystemVerilog for Design (1 ½ days)

The SystemVerilog data type system

enum • typedef • struct • union • packed/unpacked • packages and $unit • using arrays in SystemVerilog • array and structure literals, assignment patterns

Nets and variables

Key changes in Verilog-2005 and SystemVerilog • continuous assignment to variables • modified driver and connection rules • data types on ports and nets

Modules and processes

Port connection shorthand • type parameters • synthesis idioms for processes • miscellaneous improvements to the language

Design applications of interfaces

The interface construct • interfaces to encapsulate communication • modports • synthesis of interfaces and modports • imported functions for design

Fundamentals of SystemVerilog for Verification (½ day)

Key features of the SystemVerilog data type system

enum • typedef • struct • union • packed/unpacked • packages

Nets and variables

Key changes in Verilog-2005 and SystemVerilog

Testbench applications of interfaces

The interface construct • modports

SystemVerilog Assertions (½ day)

Introduction to assertions

Assertions, properties, sequences • clocking and sampling • property implication • uses of assertions • simulation of assertions • formal tools

Assertion methodology

Methodology consequences of assertion-based design and verification • assertion and assumption • benefits of assertions to the designer • protocol checkers

A brief introduction to SVA syntax

Writing simple assertions of your own • sequences and the ## operator • repetition and time ranges • sequence fusion • overview of temporal operators • local variables and actions in assertions

Packaging Assertions

Assertions in interfaces and modules • the bind construct • deploying verification IP, particularly assertion-based IP

Module-based SystemVerilog Verification (1 day)

Verification for design teams

Bus functional models • testbench architecture in classic Verilog • stimulus and response timing

Using SystemVerilog to construct module-level testbenches

Clocking and program blocks • testbench applications of interfaces • building libraries of stimulus patterns (sequences) • writing test cases to control the testbench • imported and exported subprograms

Dynamic data types

strings • queues • dynamic arrays • associative arrays • queue and array methods • foreach loop

Testbench automation

Brief introduction to testbench automation concepts • randomisation, checking and coverage • the need for constraints • randomisation of stimulus data using std::randomize and traditional Verilog distribution functions

Class-based SystemVerilog Verification (2 days)

Introducing classes

SystemVerilog's class syntax • describing stimulus data and a stimulus generator • randomization of class members (without constraints) • objects and references • constructors and new • shallow copy using new • writing a custom copy method

Hooking classes to the DUT

Dynamically-constructed test environment vs. statically-elaborated DUT and test harness • using virtual interface and class-based BFMs • the role of clocking and program blocks • appropriate structure for DUT, clock generators and other structural elements • constructing and launching the test environment using program+initial • simple class-based testbench architecture

Advanced object-oriented features

Using inheritance to extend data classes • type parameterisation of classes • using virtual methods and polymorphism to create generic testbench infrastructure such as channels, FIFOs, scoreboards • deriving custom classes from generic base classes in a library such as AVM or VMM

Constrained randomisation

Full details of the SystemVerilog randomisation machinery, including inline and declarative constraints • dynamic control of constraints • using constraints as checkers • procedural randomisation: randcase, randsequence • control fields in classes for flexible constraints • constraints and inheritance

Modelling techniques

Process control in SystemVerilog: new forms of fork..join • spawning long-running threads with fork..join_none • other modelling support: built-in classes for linked-list, semaphore, mailbox • writing checkers and behavioural reference models

Class-based testbench architecture

Layered architectures - moving verification to higher levels of abstraction • relation between layering and self-contained verification IP • approaches taken by vendor-advocated methodologies (AVM, DTV, VMM) • moving transactions around a testbench • unifying ideas: transaction ports, transaction FIFO, design pattern for publisher/subscriber, callbacks for snooping and error injection • base classes for transaction, transactor, environment • automating the activity of testbench components

Coverage and planning

Coverage-driven TBA methodology • coverage planning as the first step in a verification process • SystemVerilog coverage constructs in detail • analysing and interpreting coverage data

Adopter Classes )

Each of these classes provides a quick-start, practical introduction to one of the vendor-advocated verification methodology approaches that are rapidly gaining popularity in the SystemVerilog verification community. They can be presented as a 2-3day class giving hands-on experience of the chosen methodology, or ˝ to 1-day overview to introduce the key ideas and benefits. They are designed for use within the context of Doulos team-based SystemVerilog verification training, but can also be used stand-alone.

• OVM Adopter Class
• AVM Adopter Class
• URM Adopter Class
• VMM Adopter Class

No public course dates are currently scheduled

Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

Price on request

Back to top