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AVM Adopter Class

Advanced Level - 2 days
In-house training only

 Auf Deutsch


The Mentor Graphics® Advanced Verification Methodology (AVM) is a non-proprietary functional verification methodology implemented in both SystemVerilog and SystemC. The source code and documentation are freely available under an open-source Apache license. The scope of the AVM includes constrained random stimulus generation, functional coverage collection, assertions, and transaction-level modelling. The open structure and standard transaction-level interfaces of the AVM make it suitable for building both very simple and very complex functional verification environments.

Delegates for this course must start from a working knowledge of SystemVerilog. This course takes delegates through to full SystemVerilog verification project readiness by focussing on the verification principles and the in-depth practical application of the AVM using Mentor Graphics Questa™Sim.

Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. During the hands-on workshops, delegates will build a complete AVM verification environment for a small example system.

Who should attend?

  • Verification engineers who wish to deploy complex SystemVerilog verification environments based on the AVM
  • Design engineers who wish to make full use of SystemVerilog's verification capabilities for test bench development using the AVM

What will you learn?

  • The principles of effective functional verification using SystemVerilog
  • How to exploit the AVM libraries, classes, documentation and examples
  • How to build complete, powerful, reusable class-based AVM verification environments

Pre-requisites

A basic working knowledge of SystemVerilog is essential. For engineers with no SystemVerilog knowledge or experience the Doulos Comprehensive SystemVerilog course or equivalent is an essential precursor.

For in-house courses, precursor training in SystemVerilog can be tailored to the specific team profile (see Modular SystemVerilog). Contact Doulos to discuss options that suit your needs.

Course materials

Doulos course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:
  • Fully indexed course notes creating a complete reference manual
  • Lab files comprising the complete SystemVerilog source files and scripts

Structure and Content

Introduction

Course structure • motivation • principles • benefits • The AVM Cookbook, libraries and examples • Apache license • graphical notation • test bench organisation • operational domain versus analysis domain • AVM base classes • required / provided interfaces • naming conventions

Verification Methodology

Assertion based verification • functional coverage • structural coverage • constrained random • coverage-driven verification • the verification process • verification planning • test plans • coverage models

Class OOP-Primer

Object-Oriented Programming • class • object • method • constructor • extends • inheritance • overriding • virtual method • up-cast • parameterised class

The AVM Machinery

Class-based component hierarchy • ports and exports • connect • import_connections • export_connections • avm_named_component • avm_env • avm_report • avm_threaded_component • linking to the DUT • virtual interfaces • simulation phases • Lab - simple verification environment

Analysis Ports

avm_transaction • avm_analysis_port / export • connecting analysis ports and exports

Checkers & Scoreboards

Structural versus protocol assertions • reference models • property-based transaction generation • monitors • scoreboards • avm_in_order_comparator • avm_algorithmic_comparator • report actions • log files • configure and report phases • separating tests from test fixtures • Lab - creating a scoreboard

Functional Coverage

Separating data gathering from coverage analysis • property-based coverage • property variables and actions • covergroup and coverpoint • cross coverage • binning • analysis interface • avm_subscriber · analysis ports and virtual interfaces • coverage on internal states of DUT • Lab - creating a coverage collector

Constrained Randomization

Constrained random stimulus • tlm_fifo • standard blocking and non-blocking interfaces • put / get / peek • constraints in SystemVerilog · controlling the constraint solver • Lab - constrained random stimulus

Stimulus and Factories

avm_transaction methods • avm_random_stimulus • overriding stimulus generation • factory pattern • configuring multiple tests • random seeds • Lab - using avm_random_stimulus

Verification Environment Interactions

tlm_fifo and analysis ports • customising the report formatter • report severity and actions • report hooks • test controllers • error injection • child process control • module-based AVM environments • monitor modules • Lab - test controllers and error injection

Addendum

Reusable verification components • sequence generation • multi-channel sequence generation • test configuration randomisation • Lab - multi-channel sequence generation

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