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URM Adopter Class

Advanced Level - 2 days
In-house training only

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 Auf Deutsch


The Cadence Universal Reuse Methodology (URM) is a functional verification methodology that is based on the established e Reuse Methodology (eRM) but is also implemented in SystemVerilog and SystemC. It forms part of the Cadence Incisive Plan-to-Closure Methodology (IPCM). This course teaches how the "URM SystemVerilog Module-Based with Classes" verification methodology can be used to create high-quality, reusable verification environments. It is not intended to fulfil the deeper requirements of verification specialists who wish to exploit the class-based verification features of SystemVerilog or to interface to e and SystemC UVCs. This module-based SystemVerilog approach is also known as the Design Team Verification Methodology.

Delegates for this course must start from a working knowledge of SystemVerilog. This course takes delegates though to full SystemVerilog verification project readiness by focussing on the verification principles and the in-depth practical application of the URM.

Workshops comprise approximately 50% of class time, and are based around carefully designed exercises using the Cadence IncisiveŽ Design Team Simulator to reinforce and challenge the extent of learning.

Who should attend?

  • Design engineers who wish to make use of SystemVerilog's verification capabilities for test bench development using the URM
  • Verification engineers aiming to deploy coverage driven SystemVerilog verification environments based on the URM
  • Verification engineers who wish to create SystemVerilog verification components that are compatible with the URM (also known as Universal Verification Components - UVCs)

What will you learn?

  • The principles of effective functional verification using SystemVerilog
  • How to build complete, powerful, reusable module-based URM verification environments
  • How to exploit the URM utilities library, documentation and examples

Pre-requisites

A basic working knowledge of SystemVerilog is essential. For engineers with no SystemVerilog knowledge or experience the Doulos SystemVerilog for Design Groups course or equivalent is an essential precursor.

For team-based courses, precursor training in SystemVerilog can be tailored to the team's specific profile using our Modular SystemVerilog portfolio. Contact Doulos to discuss options that suit your needs.

Course materials

Doulos course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:
  • Fully indexed course notes creating a complete reference manual
  • Workbook full of practical examples and solutions to help you apply your knowledge

Structure and Content

Introduction to design team verification and URM

Testbench architecture • bus functional models • communication using tasks and functions with interfaces • master and slave agents

Programs and clocking blocks

SystemVerilog scheduling semantics • program blocks • clocking blocks • stimulus and response timing • program-based test and task-based test considerations

Data types for transaction-level models

strings • dynamic arrays • queues • associative arrays • queue and array methods • foreach loop

Testbench automation

Brief introduction to testbench automation concepts • randomisation, checking and coverage • the need for constraints • randomisation of stimulus data using std::randomize and traditional Verilog distribution functions

Classes for stimulus

Transaction class • objects and references • initialisation and constructors • static and constant data members • randomization of class members (without constraints) • shallow copy using new • writing a custom copy method • using inheritance to extend data classes

Randomisation and constraints

Full details of the SystemVerilog randomisation machinery, including inline and declarative constraints • dynamic control of constraints • checking constraints are met • constraint expressions • controlling distribution • constraints and inheritance • pre_randomize and post_randomize

Modelling techniques

Sequences and sequence drivers • SystemVerilog processes and process control • using SystemVerilog events • semaphore and mailbox classes • checker modules

Coverage and planning

Coverage-driven TBA methodology • coverage planning as the first step in a verification process • SystemVerilog coverage constructs in detail • creating checker modules • analysing and interpreting coverage data

Reusable testbench architecture

URM environment module • URM utility package • agents and parameters • Universal Verification Component (UVC) requirements • verification packages and libraries

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