Modular SystemC

In-house Training Options

 Auf Deutsch


Modular SystemC is a set of 4 modules related to SystemC™ (IEEE 1666-2005) aimed at fulfilling team-based training requirements for engineers from a range of technical backgrounds, i.e. hardware and software engineers and system architects. Presented from a vendor independent perspective, but supporting a wide range of EDA tools, Modular SystemC is only available for in-house or customer dedicated training.

Doulos has a world-wide lead in independent SystemC know-how having been active in SystemC-based methods since 2000. We have delivered SystemC training and support to engineers in more than 170 companies world-wide - including direct involvement with methodology and tool developers in such companies as ARM, Cadence, CoWare, Mentor Graphics and Synopsys. Modular SystemC has been developed by the authors of the IEEE 1666™ SystemC® Language Reference Manual and the TLM-2.0 User Manual.

Effective use of SystemC for modeling requires a 3-step learning path to acquire the necessary skills. A fourth module is available for engineers wishing to use SystemC for verification.

• Step 1 - Essential C++ for SystemC (2 days) takes engineers who have a basic knowledge of the C programming language and gives them a fast-track way to acquire a good grounding in C++, which is an essential foundation for learning SystemC. Engineers wanting a more complete understanding of C++ should consider the 5-day Comprehensive C++ class.
  
• Step 2 - Fundamentals of SystemC (3 days) builds on the foundation laid by Essential C++ to teach engineers the SystemC language. It describes the core SystemC v2.2 class library and its application for systems, communication, hardware and software at the transaction-level, and refinement towards hardware-software implementation.
• Step 3 - SystemC Modeling Using TLM-2.0 (3 days) builds on the foundation laid by the Fundamentals of SystemC to prepare the engineer for practical project readiness using transaction-level with SystemC and TLM-2.0.
• Expert SystemC Verification (2 days) teaches the use of SystemC for testbench automation using a constrained random verification methodology. This course, supporting version 1.0p2 of the SystemC Verification Library (SCV) teaches delegates how to debug and validate models, and exploit the library. It requires excellent C++ knowledge.

Customizing your SystemC training

Based on these modules, team-based and in-house training can be customised to fit the content, scope and duration needed to best-fit a specific customer requirement. In particular, the following SystemC topics can be emphasised:

• Hardware synthesis from SystemC, including both RTL and behavioural synthesis
• An in-depth focus on the mechanisms used in the SystemC class libraries. This is aimed at specialists who wish to develop their own channel models and at those integrating the SystemC classes into other simulation environments.
• Using the SystemC Verification library (SCV)
• Building a transaction level model of a typical bus-based platform with multiple masters at various levels of abstraction (PV, PVT, CA etc)

Workshops comprise approximately 50% of class time and are based around carefully designed exercises to reinforce and challenge the extent of learning. They can be provided in the context of the customer's choice of tools, and supplemental tool training can be arranged by Doulos, in collaboration with specific vendors, if required.

Who should attend?

• Hardware design engineers who wish to become skilled in the practical use of SystemC for digital hardware design and verification.
• System engineers and architects who wish to become skilled in the practical use of SystemC for system level modelling.
• Software engineers who already have good knowledge of C/C++, but wish to acquire some practical experience in the use of the SystemC class libraries.
• Hardware, software and systems engineers who are familiar with the SystemC class library and want to learn to use SystemC more effectively for Transaction-Level Modelling.

Pre-requisites

• Essential C++ for SystemC - delegates need basic knowledge of the C programming language; in particular, familiarity with C functions, variables, data types, operators, and statements. Recent hands-on experience of another similar programming language such as Java, or behavioural-style HDLs is advantageous. This module is suitable for people with no previous knowledge of C++ or as a refresher for those with limited knowledge of C.
  
  
• Fundamentals of SystemC - prior attendance of the Doulos 'Essential C++' class (or equivalent) is required. Before attending, delegates with solid experience of C++ and object-oriented programming should check their knowledge against the 'SystemC C++ Pre-requisites checklist' available from Doulos. This class is suitable for electronic hardware, software or systems engineers, but in order to gain maximum benefit from this class, delegates should be active users of either a high-level software programming language (ideally C++) or a hardware description language (VHDL or VerilogŪ)
  
  
• SystemC Modeling Using TLM-2.0 - Prior attendance of Essential C++ and Fundamentals of SystemC, or equivalent (Comprehensive SystemC comprises both these modules). Hardware or embedded software engineers with a background in Verilog, VHDL or C will usually need to atttend both Comprehensive SystemC and SystemC Modeling Using TLM-2.0 within a few weeks or months. Engineers with an excellent working knowledge of C++ (or some other object-oriented programing language) may be able to fast-track some of the SystemC learning requirement.
  
  
• Expert SystemC Verification - Prior attendance of Comprehensive SystemC (or equivalent). Delegates must have a good working knowledge of C++ and SystemC. Prior attendance of the Doulos Comprehensive SystemC training course (or equivalent) is required. No previous knowledge of constrained random verification is needed, as this will be introduced during the course.

Training Materials

Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. Fees include:

• Fully indexed course notes creating a complete reference manual
• Workbook full of practical examples and solutions to help you apply your knowledge
• Doulos SystemC Golden Reference Guide for language, syntax, semantics and tips.

Structure and Content

Essential C++ for SystemC (2 days)

DAY 1

Learn about the differences between C and C++

From C to C++

The features added to C by C++ and the ANSI C-1999 standard • const • bool • Header files • Namespaces • The global and standard namespaces • Stream I/O

Functional and Pointers

Learn how functions and dynamic memory allocation have changed in C++ • Pass-by-reference • Function prototypes • Default arguments • Function overloading • Operator overloading • Static, automatic and dynamic storage • new • delete

The C++ Standard Library

Learn to make the most of the built-in standard classes • Container classes • Examples of using the standard vector class • Examples of using the standard string and stringstream classes

Classes and Objects

Learn the principles of object-based design • Information hiding • Abstract data types • Classes and objects • Public and private class members • Member functions • Scope resolution

DAY 2

Master the subtleties of object-oriented programming in C++

Class Members

Master the C++ mechanisms associated with classes • Constructors • Destructors • Copy constructors • Pointers versus objects • Friends • this • Overloading operators as members • Static members • Constant objects and members

Inheritance

Learn to exploit the power of object-oriented programming • Class relationships • Initializing sub-objects • The default constructor • Derived classes • Inheritance • Protected members • Up- and down-casting • Order of initialization

Virtual Functions

Delve deeper into object-oriented programming techniques • Overriding methods • Virtual functions • Polymorphism • Run-time type identification • Abstract base classes • Multiple inheritance

Further C++ Features

Advanced C++ features used in the SystemC class libraries • Function templates • Class templates • Implicit conversions • User-defined conversions • Exceptions Additional and more detailed topic coverage is available in Comprehensive C++.

Fundamentals of SystemC (3 days)

DAY 1

Become proficient in using the features of SystemC

Introduction to SystemC

Learn the background to SystemC and how SystemC fits into the system-level design flow • The architecture of the SystemC release • The benefits and risks of adopting SystemC • The objectives of transaction-level modelling

Getting Started

Learn how SystemC source code is structured and how to organise files • SystemC header files and namespaces • Compiling and executing a SystemC model

Modules and Hierarchy

How to describe the structural connections between modules • Modules • Ports • Processes • Signals • Methods • Primitive channels • Module instantiation • Port binding

Processes and Time

Describing concurrency and the passage of time • SC_METHOD • SC_THREAD • Event finders • Static and dynamic sensitivity • Time • Events • Clocks • Dynamic processes

The Scheduler

Gain an insight into how SystemC manages the scheduling of processes and events • Starting and stopping simulation • Elaboration and simulation callbacks • The phases of simulation • Event notification • Event queues • wait and next_trigger

DAY 2

Learn to apply SystemC to modelling data, communication and busses.

Debugging and Tracing

Learn about the facilities provided by SystemC to ease debugging and diagnostics • Debugging techniques • The standard reporting mechanism • Error handling • Writing trace (vcd) files • Tracing buried signals and local variables • Using waveform display tools

SystemC Data Types

Data types for bit-accurate and hardware modelling • Signed and unsigned integers • Limited and finite precision integers • Assignment and truncation • Type conversion • Bit and part selects • Concatenation • Bit and logic vectors • Hexadecimal numbers • Avoiding common pitfalls • Bus resolution • Fixed point types

Interfaces and Channels

Learn how channels are used to abstract communication and create fast simulation models • Hierarchical, primitive and minimal channels • Interface method calls • SystemC interfaces • Port-less channel access • The SystemC object hierarchy • The class sc_port • Registering ports • How to make the most of ports, channels and interfaces

DAY 3

Exploration of the application of Transaction-Level Modelling

Bus Modelling

Learn the techniques required to write and use bus models in SystemC • Master and slave interfaces • The execution context of interface method calls • Blocking and non-blocking methods • Using events and dynamic sensitivity within channels • Multi-ports • Port binding policies • sc_export

Refinement

An example of refinement from a C algorithm through untimed and timed SystemC models down to a mixed hardware-software implementation • SystemC wrappers • Timing annotation • Using sc_buffer • Structural refinement, communication refinement, and data refinement

Adapters

Channel refinement using adapters • Events versus event finders • Instantiating and binding adapters

Transaction-Level Modeling

The OSI Transaction-Level Modeling Standards • TLM-1.0 method calls • Unidirectional interfaces • TLM-2.0 requirements • Abstraction levels • Use cases • Coding styles • The architecture of TLM-2.0 • The interoperability layer • Utilities • Initiators, targets, and interconnect • Generic payload • Extensions

Supplementary Subjects

Fixed Point Types

Fixed point word length and integer word length • Quantization modes • Overflow modes • Fixed point context • The type cast switch • Utility methods

Overview of SystemC Synthesis

RTL versus behavioural synthesis technology • The work of the OSCI synthesis working group • Synthesizable data types • Clocked threads and resets • Restrictions

Overview of the SystemC Verification Library

Introduction to and aims of SCV • Constrained random verification methodology • Extended data types to support introspection • Randomization • Transaction Recording

SystemC Modeling Using TLM-2.0 (3 days)

DAY 1
Introduction

Role of SystemC and TLM • Evolution of TLM within OSCI • TLM requirements and use cases • Coding styles • TLM-2.0 structure and architecture • Interoperability layer • Utilities • The OSCI TLM-2.0 release kit and documentation

TLM-1.0

Modeling principles • Blocking versus non-blocking interfaces • Unidirectional interfaces • Bidirectional interfaces • Request and response objects • Convenience ports • TLM FIFO interfaces • Request-response channel

TLM-2.0 Architecture

Initiators, targets, and interconnect • Initiator and target sockets • Pass-by-reference • Forward and backward paths • TLM-2 core interfaces • Blocking versus non-blocking transport • Standard socket classes • Socket binding • Introduction to the generic payload and base protocol

Blocking Transport Interface

Blocking transport interface • Timing annotation • Temporal decoupling • Quantum keeper • Global quantum • Synchronization-on-demand • Loosely-timed coding style

DAY 2

Generic Payload

Generic payload attributes • Mutability • Command, address and data attributes • Byte enables • Streaming • Response status • Generic payload memory management

Non-blocking Transport Interface

Non-blocking transport interfaces • tlm_sync_enum • Forward, backward and return paths • Phases • AT timing model • Base protocol rules • Early completion • Pre-emption • AT timing annotation • Payload event queues • Approximately-timed coding style • Request and response exclusion rules • Back-pressure • AT interconnect

Convenience Sockets

Simple sockets • b/nb conversion • Tagged sockets • Multi-sockets • Coding interconnects and address translation • Hierarchical binding • Passthrough sockets

Direct Memory and Debug Transport Interface

Direct memory versus debug interfaces • Direct memory interface • DMI transaction type • DMI descriptor • Rules for granting and denying DMI • Generic payload DMI hint • Address translation for DMI transactions • Debug transport interface • Debug transport transaction type

DAY 3

Extensions

Kinds of extension · The extension mechanism • Generic payload extension methods • Extension base class • Low-level extension programming • deep_copy_from • update_extensions_from • Extension memory management • Auto extensions • Sticky extensions • Memory-manager-agnostic extensions • Instance-specific extensions

Endianness

TLM-2 endianness principles • Organisation of the data array • Mixed-endian systems • Address alignment issues • Part-word transfers • Width conversions • Endianness helper functions • Endianness conversion functions • Arithmetic mode • Byte order mode • Tuning for simulation speed

Protocol types

tlm_phase • Extended phases • Ignorable phases • Protocol types • tlm_base_protocol_types • Defining new traits classes • Guidelines for protocol creation • Bridges • Bus snooping using DMI extensions

Analysis ports

Analysis interface • Analysis port • Subscribers • When to deep-copy transaction objects

Other examples

Source code examples to use in your own projects • AT initiator types • AT target types • Permutations of the forward, backward and return paths • Full AT interconnect implementation • Implementing exclusion rules and transaction queuing • Mixed AT/LT components • Base protocol checker • Atomic operations and transaction locking using extensions

Expert SystemC Verification (2 days)

Verification Methodology

Black and White Box Testing • Simulation and coverage • Verification Methodology Overview • What is Testbench Automation? • How SystemC and SCV fit in to verification • Obtaining SCV

Data Introspection

Extensions to data • Static vs Dynamic extensions • Extensions components • Extending built-in data types • Extending User Defined Data Types • User-defined data types with private attributes • Accessing Static Data Extensions

Randomization

Randomization • Dynamic extensions • Shared (reference-counted) pointers • Smart Pointers • Randomizing user defined data • Weighted distributions using bags • Weighted distributions using keep • Reproducibility • Using Seed Files

Constraints

Why we need constraints • Hard vs Soft • Creating constraints - scv_constraint_base • Constraining a simple data type • Constraining a user data type • Enabling and disabling constraints • Methods vs attributes • Overloading next() • Hierarchical Constraints

Transaction Recording

Requirements for transaction recording • Stream, generators, databases • Creating output • Transaction attributes • Using the transaction database

Other SCV Features

Using SCV_REPORT • The HDL Connection API • SCV data types (scv_sparse_array)

SystemC 2.1 Dynamic Threads

Dynamic Thread Applications • Spawning Threads and Methods • Setting spawn options • Spawning functions • Spawning member functions • scx_barrier

Cadence Verification Extensions (CVE) [optional]

CVE Wizards • Connecting to ncsim • Recording to an SDI database • Dynamic Thread Creation • Other data types (smart queues) Back to top