Introduction to SystemVerilog

Foundation Level - 1 days

view dates and locations
SystemVerilog is an extension to the VerilogŪ language, which enables the modelling and verification of systems at a high level of abstraction. It adds a significant set of language enhancements on top of the Verilog 2001 standard, including features for high-level, abstract system modelling, testbench automation, and the integration of Verilog with the C programming language.

Objective

This one-day seminar will provide an overview and introduction to the SystemVerilog language, explaining its background, purpose and benefits. The focus is on giving key technical staff an appreciation of how SystemVerilog can help to exploit the emerging set of verification tools and methodologies.

Who should attend

• Technical managers
• Engineering team leaders
• Engineers

This seminar is aimed at technical staff responsible for evaluating the use of the SystemVerilog language for hardware and system-level design and verification.

Pre-requisites

Prior knowledge of Verilog, VHDL or C would be of benefit, but is not a requirement.

Topics Covered

• Hardware Design Languages, Hardware Verification Languages, and System-Level Design Languages: understanding the jargon.
• Understanding the requirement for a next-generation verification language and the tools and methods it must support, including simulation, transaction-level modelling, formal verification, constrained random test generation and assertion-based verification.
• The continuing development of the Verilog language: IEEE Std 1364–1995 and 1364–2001, Superlog, SystemVerilog 3.0 and 3.1
• Accellera’s verification roadmap, including: The Design Assertion Subset (DAS), Open Verification Library (OVL), Property Specification Language (PSL), OpenVera Assertions (OVA), SystemVerilog Assertions (SVA), and Unified Assertions
• SystemVerilog as a natural successor to Verilog-1995 and Verilog-200. The new language features in SystemVerilog 3.0 and 3.1 which provide for more efficient coding.
• Communication-oriented design. How SystemVerilog interfaces can be used to improve the structure of system-level models, and how transaction-level modelling
• Test benches. How SystemVerilog allows the efficient coding of reactive test benches for constrained random test generation and functional coverage analysis
• Assertion-based verification. How SystemVerilog supports the writing of assertions as simulation checkers, and how SystemVerilog will be integrated with Accellera’s Property Specification Language for simulation and formal verification.
• Object-oriented programming. How SystemVerilog opens up the possibility of an object-oriented programming style for abstract system-level modelling and test bench writing.
  
  

  No public course dates are currently scheduled

  Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.

  
  

  Price on request

  
  Back to top