VHDL-AMS Workshop

Standard Level - 2 days

Auf Deutsch

VHDL-AMS Workshop is an intermediate 2-day course covering the extensions to VHDL for analogue and mixed-signal modelling. Available for in-house delivery only, the syllabus covers the VHDL-AMS language features, with examples of electronic circuits and systems. The new constructs are explained with reference to circuit simulation algorithms.

For engineers with little or no VHDL knowledge, a 4 day training option is available comprising a 2 day 'Introduction to VHDL' module and the VHDL-AMS Workshop.

The course is split between interactive classroom-style lectures and practical hands-on exercises using a commercial simulation tool. The workshops are carefully designed to reinforce the material presented, and illustrate the scope of the language, with interesting exercises.

Who should attend?

Engineers who have already acquired some practical experience in the use of VHDL, and who wish to extend their knowledge to the modelling of analogue and mixed-signal electronic circuits.

What will you learn?

The essential syntax of the VHDL-AMS language.

The semantics of VHDL-AMS with respect to circuit and mixed-signal simulation.
How to model basic electronic components.
How to model larger mixed-signal systems.
How to model at both circuit level and signal-flow level.
How to combine VHDL-AMS models with legacy models.

Pre-requisites

A basic knowledge of VHDL is required. Engineers new to VHDL will need to attend the 4-day training option, which includes a 2 day introductory module on VHDL. Knowledge of SPICE or other analogue simulation tools would be advantageous, but is not essential. Some basic circuit theory will be used and a familiarity with the general concepts (such as Kirchhoff's laws) would be helpful.

Course materials

Doulos Course materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. Course fees include:

Fully indexed course notes creating a complete reference manual
Workbook full of practical examples to help you apply your knowledge This includes a tool tour guide (to support the VHDL-AMS simulation tool used in the practical sessions).

Structure and Content

Introduction

Review of VHDL 1076-1999 • Maths package 1076.2 • Signal flow modelling in VHDL • 1076.1 (VHDL-AMS) Background

Nature, Terminal, Quantity

Definition of a nature • Terminal nodes • Free quantities • across and through quantities • Electrical package

Simultaneous statements

Simultaneous statements • Implicit quantities • Solvability • Simultaneous if and case statements • Examples: resistor, capacitor, diode

Netlists

Terminal and quantity ports • Component instantiation • Signal flow modelling

Procedural statements

Sequential programming constructs • Equivalent simultaneous statements • Equivalent functions • Examples: MOSFET, Opamp

Mixed-Signal simulation cycle

Simulation cycle • Initialisation • Break statements • Time step control • Frequency and Noise domain modelling

Mixed-Signal modelling

Mixing concurrent and simultaneous constructs • Events • Examples: ADC, DAC

Pros and Cons of VHDL-AMS

Limitations • Future of VHDL • Object-oriented VHDL • Future of VHDL-AMS

No public course dates are currently scheduled

Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.