Verification Methodology Manual for SystemVerilog

The Verification Methodology Manual for SystemVerilog is a professional book co-authored by verification experts from ARM Ltd. and Synopsys, Inc. and published by Springer Science and Business Media (ISBN 0-387-25538-9).

It describes a methodology suitable for verifying complex designs using SystemVerilog. It contains a wide-ranging set of rules and recommendations for constructing testbenches and test suites, for the use of assertions in verification, for making use of legacy testbench code and for system-wide verification strategy.

The building blocks of the methodology are a set of base classes which describe the important elements of a testbench:

• vmm_data for data objects and/or transactions
• vmm_xactor for the functional blocks of the testbench (transactors)
• vmm_channel (and related classes vmm_broadcast vmm_scheduler) for transactor communication
• vmm_log and vmm_notify for recording activity and inter-process communication.
• vmm_atomic_gen and vmm_scenario_gen for stimulus generation
• vmm_env to describe the structure of a particular testbench.

The example system here describes an example data type packet_trans. An atomic generator produces a number of instances of packet_trans which are fed through a channel to a transactor. This is connected to a physical interface to a simple DUT (containing 8 registers!).

Each time the generator produces a data item, a callback is used to perform an action. In this simple case it merely calls the display() method of the data object, but it can be used to modify, drop or insert data.

The set of files includes a simple shell script to compile the example.

It has been tested with Synopsys VCS® Y-2006.06.

The VMM for SystemVerilog Companion Guide, published by Doulos, is a handy quick reference for users of the Verification Methodology Manual (VMM) for SystemVerilog. You can download the complete code example mentioned in the Companion Guide from the link below.