The Universal Verification Methodology

At Last, One Functional Verification Methodology for Everyone!

Updated for UVM 1.0

The UVM 1.0 release was made available by Accellera for download on 28 Feb 2011 with the explicit endorsement of all the major simulator vendors. Now, at last, we have one single SystemVerilog verification methodology that really is supported by all EDA vendors.

The source code for the 1.0 release, now known as the UVM Base Class Library (BCL), evolved from the UVM Early Adopter release, which in turn was based on OVM version 2.1.1. The most obvious difference between OVM and UVM-EA was that all occurrence of the prefix "ovm_" were quite literally replaced with "uvm_", "OVM_" by "UVM_", "tlm_" by "uvm_tlm_", and so forth. The UVM-EA kit included a script to convert existing OVM source code. UVM-EA added a few new features on top of OVM 2.1.1, which itself added a few new features to OVM 2.0. Since OVM 2.0, the most noticeable additions have been:

• An end-of-test objection mechanism to ease the task of cleaning up at the end of a verification run
• A callback mechanism that provides an alternative to the factory for customizing behavior
• A report catcher to ease the task of customized report handling
• A heartbeat mechanisms to monitor the liveness of verification components.

You can find examples of these new features on the pages, papers, and videos referenced at the end of this page.

The UVM 1.0x releases add the following features to the Early Adopter release

• Register layer, based on the Register Abstraction Layer of VMM
• Phasing extensions, meaning a subdivided run phase, user-defined phases, and user-defined relationships between phases
• Sequence mechanism cleaned up, with the old sequence and sequencer macros deprecated
• TLM-2.0 interfaces, based on the SystemC TLM-2.0 standard
• Resource database, improving on the old set_config interface
• End-of-test mechanism cleaned up
• Command line processor, to give access to command line arguments

If you are already using the most recent features of OVM, you should beware that the implementation of the objection mechanism and callbacks has changed somewhat between OVM 2.1.1 and UVM, so UVM is not strictly backward compatible with OVM 2.1.1. Similarly, if you are already using the UVM-EA release, you will find that the 1.0 release is not strictly backwards compatible, although the changes required to your source code to run UVM-EA code on UVM 1.0 are minor.

The above feature list is not the end for UVM. Accellera are committed to an ongoing program of enhancements to UVM.

• Visit the UVM community webpage
• Download UVM 1.1 from Accellera

UVM Resources

Note: Registration many be required to access some of these resources (See Privacy Policy)

	UVM Verification Primer - an introductory tutorial on UVM.
	From OVM to UVM: Getting Started with UVM - a first example
	Easier UVM - a tutorial for VHDL and Verilog Users
	Easier UVM for Functional Verification by Mainstream Users - the paper and recording as presented at DVCon 2011
	Easier UVM - a list of upcoming and recorded webinars
	Easier SystemVerilog with UVM: Taming the Beast - the paper presented at DVCon 2012
	UVM: Now or Never? - the reasons you should (or should not) be adopting UVM right now
	First Steps with UVM: Part 1 - a simple, complete UVM source code example which you can download
	First Steps with UVM: Part 2 - showing how to drive pins on the design-under-test
	First Steps with UVM: Part 3 - showing how to use a sequencer to generate transactions
	How Much SystemVerilog Training Do You Need? - explains how to choose the right training

UVM Golden Reference Guide

The UVM Golden Reference Guide was published at DAC 48 in June 2011.

You can find out more about it and purchase the guide on-line in the Doulos Web Shop