What is SystemVerilog?

SystemVerilog has been called the industry's first Hardware Description and Verification Language (HDVL), because it combines the features of Hardware Description Languages such as Verilog and VHDL with features from specialised Hardware Verification Languages, together with features from C and C++. System Verilog became an official IEEE standard (IEEE 1800™) in 2005, and is now in the process of being further refined under the guidance of Accellera as tool vendors and users gain experience with the practical implementation and application of the language.

As it matures, SystemVerilog is finding practical application in the areas of concise and productive RTL coding, Assertion Based Verification, and building coverage-driven verification environments using constrained random techniques.

For the latest information, please visit the SystemVerilog, Accellera and IEEE 1800™ web sites.

For information about the Verilog HDL see the Verilog KnowHow section.