The Designer’s Guide to Verilog
The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.
Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer's perspective. We also provide some useful tips and pointers to other Verilog information on the web site.
Useful Verilog Tips
Design Tips
These articles are not all Verilog-specific but are certainly relevant to engineers using Verilog.
Verilog Backgrounder
A short guide to the nature and origins of Verilog:
- What is Verilog?
- A Brief History of Verilog
- Design Flow using Verilog
- Levels of Abstraction
- Scope of Verilog
- Synthesizing Verilog
Designing Hardware using Verilog
A tour of the features of Verilog that would be used in most projects. This is intended only as a brief introduction, and would not replace attendance of Comprehensive Verilog.
- A Simple Design
- Wires
- Wire Assignments
- A Design Hierarchy
- Test Benches
- Response Capture
- RTL Verilog
- If statement
- Synthesizing Latches
