The Designer’s Guide to Verilog

The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.

Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer's perspective. We also provide some useful tips and pointers to other Verilog information on the web site.

Verilog Backgrounder

• What is Verilog?
• A Brief History of Verilog
• Design Flow using Verilog
• Levels of Abstraction
• Scope of Verilog
• Synthesizing Verilog

Designing Hardware using Verilog

• A Simple Design
• Wires
• Wire Assignments
• A Design Hierarchy
• Test Benches
• Response Capture
• RTL Verilog
• If statement
• Synthesizing Latches

Useful Verilog Tips

• Sequential Always Blocks
• Think Before You Code

Other Verilog Resources

• Verilog Models
• Verilog FAQ