Tuesday 23 September 2014

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Shift Register

Well, not just a shift register. This month's model is used to highlight the creation of parameterisable components and the modelling of bidirectional ports.

The bidirectional port is modelled as a separate block from the main shifter function as a conditional continuous assignment. Notice that the high impedance state is modelled as {Length{1'bz}} rather than the more obvious Length'bz. This is because a parameter cannot be used as the vector width in Verilog. Ho hum! However, 'bz is quite legal...

The shifter function is modelled as a clocked always block The >> operator is used to present more succinct code than using concatenation would allow.

The Length parameter is used to parameterise the Data bidirectional port and the Reg register. Note that Reg is legitimate as a reg object name as Verilog is case-sensitive. But Reg is not a good name for a reg object, a better name would be shift_reg, perhaps.

So, one shift register. Parameterisable. Bidirectional. And synthesisable. Your mission, should you choose to accept it, is to modify the Verilog code to create a completely parameterisable, bidirectional shift register. Yes, bidirectional shift (shift left, as well as shift right) in addition to bidirectional I/O. This Web page will NOT self-destruct in five seconds!

You are welcome to use the source code we provide but you must keep the copyright notice with the code (see the Notices page for details).

// Shifter
//
// +-----------------------------+
// |    Copyright 1996 DOULOS    |
// |     Library: Sequential     |
// |   designer : John Aynsley   |
// +-----------------------------+

module Shifter (Clk, EN, WR, RD, SI, SO, Data);
  // synopsys template

  parameter Length = 1;

  input Clk, EN, WR, RD, SI;
  output SO;
  inout [Length-1:0] Data;

  reg SO;
  reg [Length-1:0] Reg;

  assign Data = !RD ? Reg : {Length{1'bz}};

  always @(posedge Clk)
    if (!EN)
    begin
      SO <= Reg[0];
      Reg = Reg >> 1;
      Reg[Length-1] = SI;
    end
    else if (!WR)
      Reg = Data;

  always @(WR or EN)
    if (!WR & !EN)
      $display("Error, Wr and En both active");

endmodule

To download the Verilog source code for this month's Model of the Month, click here.

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