--Component package for regfile model

library ieee;
use ieee.std_logic_1164.all;
use work.reg_file_pkg.all;

package components is

  component d_latch
  port (
    d      : in  std_logic;
    enable : in  std_logic;
    q      : out std_logic
  );
  end component;

  component demux_generic
  generic (
    in_width : integer := 1
  );
  port (
    a      : in  std_logic_vector(in_width-1 downto 0);
    enable : in  std_logic;
    y      : out std_logic_vector((2 ** in_width)-1 downto 0)
  );
  end component;

  component mux_generic
  generic (
    data_width : integer := 1;    -- N-bit data
    funnel_factor : integer := 2  -- M to 1, thus f_f = M
  );
  port (
    a   : in  std_logic_2D_array(0 to (funnel_factor-1), data_width-1 downto 0);
    sel : in  std_logic_vector;
    y   : out std_logic_vector
  );
  end component;

  component reg_file_32_8_6port is
  generic (
    num_write_ports : integer := 1;
    num_read_ports  : integer := 1;
    -- depth : integer := 32;
    -- data_width : integer := 8;
    num_bidirectional_ports : integer := 0
  );
  port (
    write    : in std_logic_vector(((num_write_ports-1) + num_bidirectional_ports) downto 0);
    read     : in std_logic_vector((( num_read_ports-1) + num_bidirectional_ports) downto 0);
    address_write : in std_logic_2D_array(2 downto 0, 4 downto 0);
    address_read  : in std_logic_2D_array(2 downto 0, 4 downto 0);
    data_in  : in  std_logic_2D_array(2 downto 0, 7 downto 0);
    data_out : out std_logic_2D_array(2 downto 0, 7 downto 0)
  );
  end component;

end package;