library IEEE;
use IEEE.std_logic_1164.all;

entity sisr is
port (
  serial_in     : std_logic;
  clock         : std_logic;
  reset         : std_logic;
  lfsr_out      : out std_logic_vector(9 downto 0);
  signature_out : out std_logic_vector(9 downto 0)
);
end sisr;

--library DFT;

architecture modular of sisr is
  --use DFT.all;

  component maximal_length_lfsr
  port (
    clock    : std_logic;
    reset    : std_logic;
    data_out : out std_logic_vector(9 downto 0)
  );
  end component;

  component signature_register
  port (
    data_in  : std_logic;
    clock    : std_logic;
    reset    : std_logic;
    data_out : out std_logic_vector(9 downto 0)
  );
  end component;

begin

  generator: maximal_length_lfsr port map (clock, reset, lfsr_out);

  analyzer: signature_register port map (serial_in, clock, reset, signature_out);

end modular;