library IEEE;
  use IEEE.std_logic_1164.all;
  use ieee.numeric_std.all;
  use std.textio.all;
  use ieee.std_logic_textio.all;


entity sisr_tb is
end sisr_tb;

architecture modular of sisr_tb is

  constant period      : time := 10 ns;
  constant half_period : time := period / 2;
  constant known_good  : integer := 166; -- when lfsr_out comes round to 1023 a 2nd time
                               -- = 824 when a(6) = '1' in faulty circuit
  constant lots        : integer := 1024;

  component sisr
  port (
    serial_in     : std_logic;
    clock         : std_logic;
    reset         : std_logic;
    lfsr_out      : out std_logic_vector(9 downto 0);
    signature_out : out std_logic_vector(9 downto 0)
  );
  end component;

  component fault_circuit is
  port (
    a : in  std_logic_vector(9 downto 0);
    y : out std_logic
  );
  end component;

  signal clock        : std_logic;
  signal reset        : std_logic;
  signal lfsr_out     : std_logic_vector(9 downto 0);
  signal serial_in    : std_logic;
  signal parallel_out : std_logic_vector(9 downto 0);

  signal timebase : integer := 0;
  -- signal lfsr10_int_sig : integer;
  -- signal lfsr10_expected_sig  : std_logic_vector(9 downto 0);
  -- signal cycle_sig : integer;

begin

  tester: sisr port map (serial_in, clock, reset, lfsr_out, parallel_out);

  dut: fault_circuit port map (lfsr_out, serial_in);
  -- suitable design is probably an adder, and select one of the outputs

  clock_gen: process
  begin
    for i in 0 to lots+7 loop
      clock <= '1';
      wait for half_period;
      clock <= '0';
      wait for half_period;
      timebase <= timebase + 1;
    end loop;
    wait;
  end process;

  sim_time: process (timebase)
  begin
    if timebase = 0 then
      reset <= '0';
    elsif timebase = 2 then
      reset <= '1';
    elsif timebase = 3 then
      reset <= '0';
    end if;
    if timebase = 1024 then -- 1024 is num of cycles where signature is known
      -- = 2 ** num_bits ???
      -- check parallel_out, is it equal to known good
    end if;
  end process;

  -- process to check ml lfsr sequence against 1023-cycle randomness - looks good
  process
    file lfsr_10 : text open READ_MODE is "lfsr_10_table.txt";
    variable lfsr10_line : line;
    -- line scratchpads for coverting to strings.
    variable tmp_line1, tmp_line2 : line;
    variable lfsr10_int : integer;
    variable lfsr10_is_good : boolean;
    variable lfsr10_expected : std_logic_vector(9 downto 0);
    -- variable message : line;
    -- variable message : line;
    variable cycle : integer := -1;
  begin
    wait until reset = '0';
    while not endfile(lfsr_10) loop
      wait on lfsr_out;
      cycle := cycle + 1;
      readline(lfsr_10, lfsr10_line);
      read(lfsr10_line, lfsr10_int, lfsr10_is_good);
      --convert lfsr10_int to a string...
      write (tmp_line1, lfsr10_int); -- was an integer
      write (tmp_line2, lfsr_out);   -- was a std_logic_vector
      if to_integer(unsigned(lfsr_out)) /= lfsr10_int then
        assert FALSE
          report (("lfsr_out not the same as lfsr10_int ... " & tmp_line1.all) & " ... ") & tmp_line2.all
          severity NOTE;
      end if;
      deallocate(tmp_line1);
      deallocate(tmp_line2);
      if timebase = 1026 then
        if to_integer(unsigned(parallel_out)) /= known_good then
          assert FALSE
            report "Error in result"
            severity note;
        else
          assert FALSE
            report "Result good."
            severity note;
        end if;
      end if;
    end loop;
    wait;
  end process;

end modular;