library IEEE;
use IEEE.std_logic_1164.all;

entity lfsr is
port (
  clock    : in std_logic;
  reset    : in std_logic;
  data_out : out std_logic
);
end lfsr;

architecture rtl of lfsr is

  signal lfsr_reg : std_logic_vector(9 downto 0);

begin

  process (clock, reset)
    variable lfsr_tap : std_logic;
  begin
    if reset = '0' then
      lfsr_reg <= (others => '1');
    elsif rising_edge(clock) then
      lfsr_tap := lfsr_reg(6) xor lfsr_reg(9);
      lfsr_reg <= lfsr_reg(8 downto 0) & lfsr_tap;
    end if;
  end process;

  data_out <= lfsr_reg(9);

end rtl;