library ieee;
use ieee.std_logic_1164.all;

entity spec_tb is end;

architecture test of spec_tb is

  signal prbs_out, RF_in: std_logic;
  signal lfsrclock, spreadclock, reset : std_logic := '1';
  signal data_out : std_logic;

  signal stop : boolean := false;

begin

  DUT : entity work.spectrum_spreader
    port map (RF_data => RF_in,
              clock   => spreadclock,
              reset   => reset,
              spread_data => data_out);

  prbs_gen : entity work.lfsr
    port map (clock   => lfsrclock,
              reset   => reset,
              data_out => prbs_out);

  RF_in <= prbs_out;

  reset <= '1', '0' after 5 ns, '1' after 15 ns;

  spreadclock_p : process is begin
    while not stop loop
      spreadclock <= not spreadclock;
      wait for 10 ns;
    end loop;
    wait;
  end process;

  lfsrclock_p : process is begin
    while not stop loop
      lfsrclock <= not lfsrclock;
      wait for 60 ns;
    end loop;
    wait;
  end process;

  stop <= true after 10 us;

end test;