A Mix Of Useful Tips
- Sequential Processes
- Design for Debug
- Writing Reference Models
- Deferred Constants
- Encapsulation in VHDL
- Avoid Synthesizing Unwanted Latches
- Re-using Code Snippets
- Re-usable Functions
- Synthesizing "+" : Part One
- Synthesizing "+" : Part Two
- Clock Generation
- Magic Numbers
- Beware those 'if' statements
- Using LUT Architectures in FPGAs
- Unrolling Loops