Tuesday 16 September 2014

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Clock Generation

In almost any testbench, a clock signal is usually required in order to synchronise stimulus signals within the testbench. A free-running clock can be created thus:

-- architecture declarative part
  signal  clock : std_ulogic := '1';
-- architecture statement part
  clock <= not clock after 5ns;

Note the use of declaration initialization for the clock signal. We need this becuase the default initialization value of a std_ulogic signal is 'U'. The first time the signal assignment executes, not 'U' is 'X' and the remaining executions (every 5 ns) of this statement yield not 'X' is 'X' - no clock sequence at all. The disadvantage of this approach is that the clock runs forever - and so will the simulation!

Rather than continuous generation, what we would like to do is implement the clock generator inside a process so that a known number of clock cycles can be generated, courtesy of a for loop.

-- architecture declarative part
  constant num_cycles : integer := 320;
  signal  clock : std_ulogic := '1';
-- architecture statement part
  process
  begin
    for i in 1 to num_cycles loop
      clock <= not clock;
      wait for 5 ns;
      clock <= not clock;
      wait for 5 ns;
      -- clock period = 10 ns
    end loop;
  end process;

Note that a VHDL constant is used to allow easy maintainance of the simulation duration. However, this piece of code doesn't really do the trick. After 320 cycles, the loop exits and the process is re-invoked, generating sets of 320 cycles continuously. In order to stop the simulation from running forever due to continuous clock cycle generation, we can append a wait statement to this process to suspend the process indefinitely after one pass of 320 cycles.

process
begin
  for i in 1 to num_cycles loop
    clock <= not clock;
    wait for 5 ns;
    clock <= not clock;
    wait for 5 ns;
    -- clock period = 10 ns
  end loop;
  wait;  -- simulation stops here
end process;

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